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CRC32C

CRC32C performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

In Armv8-A, this is an optional instruction, and in Armv8.1 it is mandatory for all implementations to implement it.

ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010sz0RnRd(0)(0)1(0)0100Rm
condC

CRC32CB (sz == 00)

CRC32CB{<q>} <Rd>, <Rn>, <Rm>

CRC32CH (sz == 01)

CRC32CH{<q>} <Rd>, <Rn>, <Rm>

CRC32CW (sz == 10)

CRC32CW{<q>} <Rd>, <Rn>, <Rm>

if ! HaveCRCExt() then UNDEFINED;
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
size = 8 << UInt(sz);
crc32c = (C == '1');
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if size == 64 then UNPREDICTABLE;
if cond != '1110' then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If size == 64, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes with the additional decode: size = 32;.

If cond != '1110', then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes unconditionally.
  • The instruction executes conditionally.

T1

15141312111098765432101514131211109876543210
111110101101Rn1111Rd10szRm
C

CRC32CB (sz == 00)

CRC32CB{<q>} <Rd>, <Rn>, <Rm>

CRC32CH (sz == 01)

CRC32CH{<q>} <Rd>, <Rn>, <Rm>

CRC32CW (sz == 10)

CRC32CW{<q>} <Rd>, <Rn>, <Rm>

if InITBlock() then UNPREDICTABLE;
if ! HaveCRCExt() then UNDEFINED;
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
size = 8 << UInt(sz);
crc32c = (C == '1');
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if size == 64 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If size == 64, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes with the additional decode: size = 32;.

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>

See Standard assembler syntax fields. An CRC32C instruction must be unconditional.

<Rd>

Is the general-purpose accumulator output register, encoded in the "Rd" field.

<Rn>

Is the general-purpose accumulator input register, encoded in the "Rn" field.

<Rm>

Is the general-purpose data source register, encoded in the "Rm" field.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();

    acc = R[n];             // accumulator
    val = R[m]<size-1:0>;   // input value
    poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>;
    tempacc = BitReverse(acc):Zeros(size);
    tempval = BitReverse(val):Zeros(32);
    // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
    R[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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