You copied the Doc URL to your clipboard.

ESB

Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state.

In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, ARMv8, for ARMv8-A architecture profile.

If the RAS Extension is not implemented, this instruction executes as a NOP.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(Armv8.2)

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00010000
cond

A1

ESB{<c>}{<q>}

if !HaveRASExt() then EndOfInstruction();  // Instruction executes as NOP
if cond != '1110' then UNPREDICTABLE;      // ESB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes unconditionally.
  • The instruction executes conditionally.

T1
(Armv8.2)

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000010000

T1

ESB{<c>}.W

if !HaveRASExt() then EndOfInstruction();  // Instruction executes as NOP
if InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes unconditionally.
  • The instruction executes conditionally.

Assembler Symbols

Operation

if ConditionPassed() then
    EncodingSpecificOperations();

    SynchronizeErrors();
    AArch32.ESBOperation();
    if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch32.vESBOperation();
    TakeUnmaskedSErrorInterrupts();
Was this page helpful? Yes No