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LDAEXD

Load-Acquire Exclusive Doubleword loads a doubleword from memory, writes it to two registers and:

  • If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor
  • Causes the executing PE to indicate an active exclusive access in the local monitor.

The instruction also acts as a barrier instruction with the ordering requirements described in Load-Acquire, Store-Release.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100011011RnRt(1)(1)101001(1)(1)(1)(1)
cond

A1

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]

t = UInt(Rt);  t2 = t + 1;  n = UInt(Rn);
if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If Rt<0> == '1', then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes with the additional decode: t<0> = '0'.
  • The instruction executes with the additional decode: t2 = t.
  • The instruction executes as described, with no change to its behavior and no additional side effects.

If Rt == '1110', then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction is handled as described in Using R15.

T1

15141312111098765432101514131211109876543210
111010001101RnRtRt21111(1)(1)(1)(1)

T1

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]

t = UInt(Rt);  t2 = UInt(Rt2);  n = UInt(Rn);
if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == t2, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The load instruction executes but the destination register takes an unknown value.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rt>

For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14.

For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>

For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address, 8);
    value = MemO[address, 8];
    // Extract words from 64-bit loaded value such that R[t] is
    // loaded from address and R[t2] from address+4.
    R[t]  = if BigEndian() then value<63:32> else value<31:0>;
    R[t2] = if BigEndian() then value<31:0>  else value<63:32>;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

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