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PLD, PLDW (immediate)

Preload Data (immediate) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.

The PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write.

The effect of a PLD or PLDW instruction is implementation defined. For more information, see Preloading caches.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
11110101UR01!= 1111(1)(1)(1)(1)imm12
Rn

Preload read (R == 1)

PLD{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]

Preload write (R == 0)

PLDW{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]

if Rn == '1111' then SEE "PLD (literal)";
n = UInt(Rn);  imm32 = ZeroExtend(imm12, 32);  add = (U == '1');  is_pldw = (R == '0');

T1

15141312111098765432101514131211109876543210
1111100010W1!= 11111111imm12
Rn

Preload read (W == 0)

PLD{<c>}{<q>} [<Rn> {, #{+}<imm>}]

Preload write (W == 1)

PLDW{<c>}{<q>} [<Rn> {, #{+}<imm>}]

if Rn == '1111' then SEE "PLD (literal)";
n = UInt(Rn);  imm32 = ZeroExtend(imm12, 32);  add = TRUE;  is_pldw = (W == '1');

T2

15141312111098765432101514131211109876543210
1111100000W1!= 111111111100imm8
Rn

Preload read (W == 0)

PLD{<c>}{<q>} [<Rn> {, #-<imm>}]

Preload write (W == 1)

PLDW{<c>}{<q>} [<Rn> {, #-<imm>}]

if Rn == '1111' then SEE "PLD (literal)";
n = UInt(Rn);  imm32 = ZeroExtend(imm8, 32);  add = FALSE;  is_pldw = (W == '1');

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

For encoding A1: see Standard assembler syntax fields. Must be AL or omitted.

For encoding T1 and T2: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see PLD (literal).

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U +/-
0 -
1 +
+

Specifies the offset is added to the base register.

<imm>

For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = if add then (R[n] + imm32) else (R[n] - imm32);
    if is_pldw then
        Hint_PreloadDataForWrite(address);
    else
        Hint_PreloadData(address);
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