You copied the Doc URL to your clipboard.

RFE, RFEDA, RFEDB, RFEIA, RFEIB

Return From Exception loads two consecutive memory locations using an address in a base register:

  • The word loaded from the lower address is treated as an instruction address. The PE branches to it.
  • The word loaded from the higher address is used to restore PSTATE. This word must be in the format of an SPSR.

An address adjusted by the size of the data loaded can optionally be written back to the base register.

The PE checks the value of the word loaded from the higher address for an illegal return event. See Illegal return events from AArch32 state.

RFE is undefined in Hyp mode and constrained unpredictable in User mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
1111100PU0W1Rn(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)

Decrement After (P == 0 && U == 0)

RFEDA{<c>}{<q>} <Rn>{!}

Decrement Before (P == 1 && U == 0)

RFEDB{<c>}{<q>} <Rn>{!}

Increment After (P == 0 && U == 1)

RFE{IA}{<c>}{<q>} <Rn>{!}

Increment Before (P == 1 && U == 1)

RFEIB{<c>}{<q>} <Rn>{!}

n = UInt(Rn);
wback = (W == '1');  increment = (U == '1');  wordhigher = (P == U);
if n == 15 then UNPREDICTABLE;

T1

15141312111098765432101514131211109876543210
1110100000W1Rn(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)

T1

RFEDB{<c>}{<q>} <Rn>{!} // (Outside or last in IT block)

n = UInt(Rn);  wback = (W == '1');  increment = FALSE;  wordhigher = FALSE;
if n == 15 then UNPREDICTABLE;
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

T2

15141312111098765432101514131211109876543210
1110100110W1Rn(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)

T2

RFE{IA}{<c>}{<q>} <Rn>{!} // (Outside or last in IT block)

n = UInt(Rn);  wback = (W == '1');  increment = TRUE;  wordhigher = FALSE;
if n == 15 then UNPREDICTABLE;
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

IA

For encoding A1: is an optional suffix to indicate the Increment After variant.

For encoding T2: is an optional suffix for the Increment After form.

<c>

For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted.

For encoding T1 and T2: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

!

The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if PSTATE.EL == EL2 then
        UNDEFINED;
    elsif PSTATE.EL == EL0 then
        UNPREDICTABLE;                        // UNDEFINED or NOP
    else
        address = if increment then R[n] else R[n]-8;
        if wordhigher then address = address+4;
        new_pc_value = MemA[address,4];
        spsr = MemA[address+4,4];
        if wback then R[n] = if increment then R[n]+8 else R[n]-8;
        AArch32.ExceptionReturn(new_pc_value, spsr);

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.EL == EL0, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
Was this page helpful? Yes No