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SSBB

Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions.

The semantics of the Speculative Store Bypass Barrier are:

  • When a load to a location appears in program order after the SSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:
    • The store is to the same location as the load.
    • The store uses the same virtual address as the load.
    • The store appears in program order before the SSBB.
  • When a load to a location appears in program order before the SSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:
    • The store is to the same location as the load.
    • The store uses the same virtual address as the load.
    • The store appears in program order after the SSBB.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)01000000

A1

SSBB{<q>}

// No additional decoding required

T1

15141312111098765432101514131211109876543210
111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)01000000

T1

SSBB{<q>}

if InITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    SpeculativeStoreBypassBarrierToVA();
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