STLEXD
Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.
The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release.
For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | Rn | Rd | (1) | (1) | 1 | 0 | 1 | 0 | 0 | 1 | Rt | ||||||||||||
cond |
d = UInt(Rd); t = UInt(Rt); t2 = t+1; n = UInt(Rn); if d == 15 || Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t || d == t2 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If d == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If d == n, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction performs the store to an unknown address.
If Rt<0> == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes with the additional decode: Rt<0> = '0'.
- The instruction executes with the additional decode: t2 = t.
- The instruction executes as described, with no change to its behavior and no additional side effects.
If Rt == '1110', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction is handled as described in Using R15.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Rn | Rt | Rt2 | 1 | 1 | 1 | 1 | Rd |
d = UInt(Rd); t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t || d == t2 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If d == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If d == n, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction performs the store to an unknown address.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
<Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
Aborts and alignment
If a synchronous Data Abort exception is generated by the execution of this instruction:
- Memory is not updated.
- <Rd> is not updated.
A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:
- If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.
- Otherwise, it is implementation defined whether the exception is generated.
If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is implementation defined whether the exception is generated.
Operation
if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4. value = if BigEndian() then R[t]:R[t2] else R[t2]:R[t]; if AArch32.ExclusiveMonitorsPass(address, 8) then MemO[address, 8] = value; R[d] = ZeroExtend('0'); else R[d] = ZeroExtend('1');
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.