STR (immediate)
Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
This instruction is used by the alias PUSH (single register).
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 1 | 0 | P | U | 0 | W | 0 | Rn | Rt | imm12 | ||||||||||||||||||||
cond |
if P == '0' && W == '1' then SEE "STRT"; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); if wback && (n == 15 || n == t) then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If wback && n == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If wback && n == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses the addressing mode described in the equivalent immediate offset instruction.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | imm5 | Rn | Rt |
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32); index = TRUE; add = TRUE; wback = FALSE;
T2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 1 | 0 | Rt | imm8 |
t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32); index = TRUE; add = TRUE; wback = FALSE;
T3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | != 1111 | Rt | imm12 | |||||||||||||||||
Rn |
if Rn == '1111' then UNDEFINED; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); index = TRUE; add = TRUE; wback = FALSE; if t == 15 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If t == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
T4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | != 1111 | Rt | 1 | P | U | W | imm8 | |||||||||||||
Rn |
if P == '1' && U == '1' && W == '0' then SEE "STRT"; if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); index = (P == '1'); add = (U == '1'); wback = (W == '1'); if t == 15 || (wback && n == t) then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If wback && n == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If wback && n == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses the addressing mode described in the equivalent immediate offset instruction.
If t == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U:
|
+ |
Specifies the offset is added to the base register. |
Alias Conditions
Alias | Of variant | Is preferred when |
---|---|---|
PUSH (single register) | A1 (pre-indexed) | P == '1' && U == '0' && W == '1' && Rn == '1101' && imm12 == '000000000100' |
PUSH (single register) | T4 (pre-indexed) | Rn == '1101' && U == '0' && imm8 == '00000100' |
Operation
if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; if wback then R[n] = offset_addr; else if ConditionPassed() then EncodingSpecificOperations(); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; MemU[address,4] = R[t]; if wback then R[n] = offset_addr;
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.