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TSB CSYNC

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions.

If the Self-Hosted Trace Extension is not implemented, this instruction executes as a NOP.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(Armv8.4)

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00010010
cond

A1

TSB{<c>}{<q>} CSYNC

if !HaveSelfHostedTrace() then EndOfInstruction(); // Instruction executes as NOP
if cond != '1110' then UNPREDICTABLE;              // ESB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes unconditionally.
  • The instruction executes conditionally.

T1
(Armv8.4)

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000010010

T1

TSB{<c>}{<q>} CSYNC

if !HaveSelfHostedTrace() then EndOfInstruction(); // Instruction executes as NOP
if InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The instruction executes unconditionally.
  • The instruction executes conditionally.

Assembler Symbols

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    TraceSynchronizationBarrier();
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