AMCNTENSET1, Activity Monitors Count Enable Set Register 1
The AMCNTENSET1 characteristics are:
Purpose
Enable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>.
Configuration
AArch32 System register AMCNTENSET1 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET1_EL0[31:0] .
AArch32 System register AMCNTENSET1 bits [31:0] are architecturally mapped to External register AMCNTENSET1[31:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET1 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Attributes
AMCNTENSET1 is a 32-bit register.
Field descriptions
The AMCNTENSET1 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| P<n>, bit [n] | |||||||||||||||||||||||||||||||
P<n>, bit [n], for n = 0 to 31
Activity monitor event counter enable bit for AMEVCNTR1<n>.
Bits [31:N] are RAZ/WI. N is the value in AMCGCR.CG1NC.
Possible values of each bit are:
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMEVCNTR1<n> is disabled. When written, has no effect. |
| 0b1 |
When read, means that AMEVCNTR1<n> is enabled. When written, enables AMEVCNTR1<n>. |
On a Cold reset, this field resets to 0.
Accessing the AMCNTENSET1
If the number of auxiliary activity monitor event counters implemented is zero, reads and writes of AMCNTENSET1 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.
The number of auxiliary activity monitor counters implemented is zero when AMCFGR.NCG == 0b0000.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1101 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMCNTENSET1;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMCNTENSET1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMCNTENSET1;
elsif PSTATE.EL == EL3 then
return AMCNTENSET1;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1101 | 0b0011 | 0b001 |
if PSTATE.EL == EL1 && EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif PSTATE.EL == EL1 && EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif IsHighestEL(PSTATE.EL) then
AMCNTENSET1 = R[t];
else
UNDEFINED;