CNTHV_TVAL, Counter-timer Virtual Timer TimerValue register (EL2)
The CNTHV_TVAL characteristics are:
Purpose
Provides AArch32 access to the timer value for the EL2 virtual timer.
The EL2 virtual timer is implemented by ARMv8.1-VHE. It is only accessible from AArch32 state when EL0 is using AArch32, EL2 is using AArch64, and the value of HCR_EL2.{E2H, TGE} is {1, 1}.
Configuration
AArch32 System register CNTHV_TVAL bits [31:0] are architecturally mapped to AArch64 System register CNTHV_TVAL_EL2[31:0] .
This register is present only from Armv8.1. Otherwise, direct accesses to CNTHV_TVAL are UNDEFINED.
Attributes
CNTHV_TVAL is a 32-bit register.
Field descriptions
The CNTHV_TVAL bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TimerValue | |||||||||||||||||||||||||||||||
TimerValue, bits [31:0]
The TimerValue view of the EL2 virtual timer.
On a read of this register:
- If CNTHV_CTL.ENABLE is 0, the value returned is UNKNOWN.
- If CNTHV_CTL.ENABLE is 1, the value returned is (CNTHV_CVAL - CNTVCT).
On a write of this register, CNTHV_CVAL is set to (CNTVCT + TimerValue), where TimerValue is treated as a signed 32-bit integer.
When CNTHV_CTL.ENABLE is 1, the timer condition is met when (CNTVCT - CNTHV_CVAL) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:
When CNTHV_CTL.ENABLE is 0, the timer condition is not met, but CNTVCT continues to count, so the TimerValue view appears to continue to count down.
Accessing the CNTHV_TVAL
This register is accessed using the encoding for CNTV_TVAL.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1110 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' then
return CNTHVS_TVAL_EL2;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then
return CNTHV_TVAL_EL2;
else
return CNTV_TVAL;
elsif PSTATE.EL == EL1 then
return CNTV_TVAL;
elsif PSTATE.EL == EL2 then
return CNTV_TVAL;
elsif PSTATE.EL == EL3 then
return CNTV_TVAL;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1110 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' then
CNTHVS_TVAL_EL2 = R[t];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then
CNTHV_TVAL_EL2 = R[t];
else
CNTV_TVAL = R[t];
elsif PSTATE.EL == EL1 then
CNTV_TVAL = R[t];
elsif PSTATE.EL == EL2 then
CNTV_TVAL = R[t];
elsif PSTATE.EL == EL3 then
CNTV_TVAL = R[t];