DISR, Deferred Interrupt Status Register
The DISR characteristics are:
Purpose
Records that an SError interrupt has been consumed by an ESB instruction.
Configuration
AArch32 System register DISR bits [31:0] are architecturally mapped to AArch64 System register DISR_EL1[31:0] when the highest implemented Exception level is using AArch64.
This register is present only when RAS is implemented. Otherwise, direct accesses to DISR are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
DISR is a 32-bit register.
Field descriptions
The DISR bit assignments are:
When the ESB instruction is executed at EL2:
A, bit [31]
Set to 1 when an ESB instruction defers an asynchronous SError interrupt. If the implementation does not include any sources of SError interrupt that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Bits [30:12]
Reserved, RES0.
AET, bits [11:10]
Asynchronous Error Type. See the description of HSR.AET for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
EA, bit [9]
External abort Type. See the description of HSR.EA for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bits [8:6]
Reserved, RES0.
DFSC, bits [5:0]
Fault Status Code. See the description of HSR.DFSC for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
When the ESB instruction is executed at EL0 or EL1 and where TTBCR.EAE == 0:
A, bit [31]
Set to 1 when an ESB instruction defers an asynchronous SError interrupt. If the implementation does not include any sources of SError interrupt that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Bits [30:16]
Reserved, RES0.
AET, bits [15:14]
Asynchronous Error Type. See the description of DFSR.AET for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bit [13]
Reserved, RES0.
ExT, bit [12]
External abort Type. See the description of DFSR.ExT for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bit [11]
Reserved, RES0.
FS[4], bit [10]
This field is bit[4] of FS[4:0].
Fault Status Code. See the description of DFSR.FS for an SError interrupt.
The FS field is split as follows:
- FS[4] is DISR[10].
- FS[3:0] is DISR[3:0].
This field resets to an architecturally UNKNOWN value.
LPAE, bit [9]
Format.
| LPAE | Meaning |
|---|---|
| 0b0 |
Using the Short-descriptor translation table format. |
This field resets to an architecturally UNKNOWN value.
Bits [8:4]
Reserved, RES0.
FS[3:0], bits [3:0]
This field is bits[3:0] of FS[4:0].
See FS[4] for the field description.
When the ESB instruction is executed at EL0 or EL1 and where TTBCR.EAE == 1:
A, bit [31]
Set to 1 when an ESB instruction defers an asynchronous SError interrupt. If the implementation does not include any sources of SError interrupt that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Bits [30:16]
Reserved, RES0.
AET, bits [15:14]
Asynchronous Error Type. See the description of DFSR.AET for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bit [13]
Reserved, RES0.
ExT, bit [12]
External abort Type. See the description of DFSR.ExT for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bits [11:10]
Reserved, RES0.
LPAE, bit [9]
Format.
| LPAE | Meaning |
|---|---|
| 0b1 |
Using the Long-descriptor translation table format. |
This field resets to an architecturally UNKNOWN value.
Bits [8:6]
Reserved, RES0.
STATUS, bits [5:0]
Fault Status Code. See the description of DFSR.DFSC for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Accessing the DISR
An indirect write to DISR made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR occurring in program order after the ESB instruction.
DISR is RAZ/WI if EL3 is implemented, the PE is in Non-debug state, and any of the following apply:
- EL3 is using AArch64, SCR_EL3.EA == 1, and any of the following apply:
- EL3 is using AArch32, SCR.EA == 1, and any of the following apply:
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
return VDISR_EL2;
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then
return VDISR;
else
return DISR;
elsif PSTATE.EL == EL2 then
return DISR;
elsif PSTATE.EL == EL3 then
return DISR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
VDISR_EL2 = R[t];
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then
VDISR = R[t];
else
DISR = R[t];
elsif PSTATE.EL == EL2 then
DISR = R[t];
elsif PSTATE.EL == EL3 then
DISR = R[t];