TTBCR2, Translation Table Base Control Register 2
The TTBCR2 characteristics are:
Purpose
The second control register for stage 1 of the PL1&0 translation regime.
If ARMv8.2-AA32HPD is not implemented then this register is not implemented and its encoding is unallocated. Otherwise:
- When the value of TTBCR.{EAE, T2E} is not {1, 1} the contents of TTBCR2 are treated as zero for all purposes other than reading or writing the register.
- When the value of TTBCR.{EAE, T2E} is {1, 1} TTBCR2 is used with TTBCR.
Configuration
AArch32 System register TTBCR2 bits [31:0] are architecturally mapped to AArch64 System register TCR_EL1[63:32] .
This register is present only from Armv8.2. Otherwise, direct accesses to TTBCR2 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
TTBCR2 is a 32-bit register.
Field descriptions
The TTBCR2 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | HWU162 | HWU161 | HWU160 | HWU159 | HWU062 | HWU061 | HWU060 | HWU059 | HPD1 | HPD0 | RES0 | ||||||||||||||||||||
Bits [31:19]
Reserved, RES0.
HWU162, bit [18]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using TTBR1.
| HWU162 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR1, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR1, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD1 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU161, bit [17]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using TTBR1.
| HWU161 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR1, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR1, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD1 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU160, bit [16]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using TTBR1.
| HWU160 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR1, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR1, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD1 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU159, bit [15]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using TTBR1.
| HWU159 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR1, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR1, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD1 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU062, bit [14]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using TTBR0.
| HWU062 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR0, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR0, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD0 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU061, bit [13]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using TTBR0.
| HWU061 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR0, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR0, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD0 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU060, bit [12]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using TTBR0.
| HWU060 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR0, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR0, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD0 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU059, bit [11]
When ARMv8.2-TTPBHA is implemented:
When ARMv8.2-TTPBHA is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using TTBR0.
| HWU059 | Meaning |
|---|---|
| 0b0 |
For translations using TTBR0, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
| 0b1 |
For translations using TTBR0, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TTBCR2.HPD0 is 1. |
The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HPD1, bit [10]
When ARMv8.2-AA32HPD is implemented:
When ARMv8.2-AA32HPD is implemented:
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by TTBR1.
| HPD1 | Meaning |
|---|---|
| 0b0 |
Hierarchical permissions are enabled. |
| 0b1 |
Hierarchical permissions are disabled if TTBCR.T2E == 1. |
When disabled, the permissions are treated as if the bits are 0.
The Effective value of this field is 0 if the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HPD0, bit [9]
When ARMv8.2-AA32HPD is implemented:
When ARMv8.2-AA32HPD is implemented:
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by TTBR0.
| HPD0 | Meaning |
|---|---|
| 0b0 |
Hierarchical permissions are enabled. |
| 0b1 |
Hierarchical permissions are disabled if TTBCR.T2E ==1. |
When disabled, the permissions are treated is as if the bits are 0.
The Effective value of this field is 0 if the value of TTBCR.T2E is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [8:0]
Reserved, RES0.
Accessing the TTBCR2
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0010 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
return TTBCR2_S;
else
return TTBCR2_NS;
else
return TTBCR2;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
return TTBCR2_NS;
else
return TTBCR2;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
return TTBCR2_S;
else
return TTBCR2_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0010 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
TTBCR2_S = R[t];
else
TTBCR2_NS = R[t];
else
TTBCR2 = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
TTBCR2_NS = R[t];
else
TTBCR2 = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
if SCR.NS == '0' then
TTBCR2_S = R[t];
else
TTBCR2_NS = R[t];