VDISR, Virtual Deferred Interrupt Status Register
The VDISR characteristics are:
Purpose
Records that an SError interrupt has been consumed by an ESB instruction.
Configuration
AArch32 System register VDISR bits [31:0] are architecturally mapped to AArch64 System register VDISR_EL2[31:0] .
This register is present only when RAS is implemented. Otherwise, direct accesses to VDISR are UNDEFINED.
If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
VDISR is a 32-bit register.
Field descriptions
The VDISR bit assignments are:
When TTBCR.EAE == 0:
A, bit [31]
Set to 1 when an ESB instruction defers a virtual SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bits [30:16]
Reserved, RES0.
AET, bits [15:14]
The value copied from VDFSR.AET.
This field resets to an architecturally UNKNOWN value.
Bit [13]
Reserved, RES0.
ExT, bit [12]
The value copied from VDFSR.ExT.
This field resets to an architecturally UNKNOWN value.
Bit [11]
Reserved, RES0.
FS[4], bit [10]
This field is bit[4] of FS[4:0].
Fault status code. Set to 0b10110 when an ESB instruction defers a virtual SError interrupt.
| FS | Meaning |
|---|---|
| 0b10110 |
Asynchronous SError interrupt. |
All other values are reserved.
The FS field is split as follows:
- FS[4] is VDISR[10].
- FS[3:0] is VDISR[3:0].
This field resets to an architecturally UNKNOWN value.
LPAE, bit [9]
Format.
Set to TTBCR.EAE when an ESB instruction defers a virtual SError interrupt.
| LPAE | Meaning |
|---|---|
| 0b0 |
Using the Short-descriptor translation table format. |
This field resets to an architecturally UNKNOWN value.
Bits [8:4]
Reserved, RES0.
FS[3:0], bits [3:0]
This field is bits[3:0] of FS[4:0].
See FS[4] for the field description.
When TTBCR.EAE == 1:
A, bit [31]
Set to 1 when an ESB instruction defers a virtual SError interrupt.
This field resets to an architecturally UNKNOWN value.
Bits [30:16]
Reserved, RES0.
AET, bits [15:14]
The value copied from VDFSR.AET.
This field resets to an architecturally UNKNOWN value.
Bit [13]
Reserved, RES0.
ExT, bit [12]
The value copied from VDFSR.ExT.
This field resets to an architecturally UNKNOWN value.
Bits [11:10]
Reserved, RES0.
LPAE, bit [9]
Format.
Set to TTBCR.EAE when an ESB instruction defers a virtual SError interrupt.
| LPAE | Meaning |
|---|---|
| 0b1 |
Using the Long-descriptor translation table format. |
This field resets to an architecturally UNKNOWN value.
Bits [8:6]
Reserved, RES0.
STATUS, bits [5:0]
Fault status code. Set to 0b010001 when an ESB instruction defers a virtual SError interrupt.
| STATUS | Meaning |
|---|---|
| 0b010001 |
Asynchronous SError interrupt. |
All other values are reserved.
This field resets to an architecturally UNKNOWN value.
Accessing the VDISR
Direct reads and writes of VDFSR are UNDEFINED if EL3 is implemented and using AArch32 in all Secure privileged modes other than Monitor mode.
An indirect write to VDISR made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR occurring in program order after the ESB instruction.
If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return VDISR;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
UNDEFINED;
else
return VDISR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
VDISR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
UNDEFINED;
else
VDISR = R[t];
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
return VDISR_EL2;
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then
return VDISR;
else
return DISR;
elsif PSTATE.EL == EL2 then
return DISR;
elsif PSTATE.EL == EL3 then
return DISR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
VDISR_EL2 = R[t];
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then
VDISR = R[t];
else
DISR = R[t];
elsif PSTATE.EL == EL2 then
DISR = R[t];
elsif PSTATE.EL == EL3 then
DISR = R[t];