HPFAR_EL2, Hypervisor IPA Fault Address Register
The HPFAR_EL2 characteristics are:
Purpose
Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.
Configuration
AArch64 System register HPFAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HPFAR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
HPFAR_EL2 is a 64-bit register.
Field descriptions
The HPFAR_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| NS | RES0 | FIPA[51:48] | FIPA[47:12] | ||||||||||||||||||||||||||||
| FIPA[47:12] | RES0 | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Execution at EL1 or EL0 makes HPFAR_EL2 become UNKNOWN.
NS, bit [63]
From Armv8.4:
From Armv8.4:
Faulting IPA address space.
| NS | Meaning |
|---|---|
| 0b0 |
Faulting IPA is from the Secure IPA space. |
| 0b1 |
Faulting IPA is from the Non-secure IPA space. |
For data or instruction aborts taken to Non-secure EL2, this field is RES0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [62:44]
Reserved, RES0.
FIPA[51:48], bits [43:40]
From Armv8.2, or if ARMv8.2-LPA is implemented:
From Armv8.2, or if ARMv8.2-LPA is implemented:
Extension to FIPA[47:12]. See FIPA[47:12] for more details.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
FIPA[47:12], bits [39:4]
Bits [47:12] of the faulting intermediate physical address.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use for the stage 1 translation, the FIPA[51:48] bits form the upper part of the address value. For implementations or stage 1 translation granules with fewer than 52 physical address bits the FIPA[51:48] bits are RES0.
The HPFAR_EL2 is written for:
- Translation or Access faults in the second stage of translation.
- An abort in the second stage of translation performed during the translation table walk of a first stage translation, caused by a Translation fault, an Access flag fault, or a Permission fault.
- A stage 2 Address size fault.
The address held in this register is an address accessed by the instruction fetch or data access that caused the exception that gave rise to the instruction or data abort. It is the lowest address that gave rise to the fault. Where different faults from different addresses arise from the same instruction, such as for an instruction that loads or stores a mis-aligned address that crosses a page boundary, the architecture does not prioritize between those different faults.
For all other exceptions taken to EL2, this register is UNKNOWN.
This field resets to an architecturally UNKNOWN value.
Bits [3:0]
Reserved, RES0.
Accessing the HPFAR_EL2
Accesses to this register use the following encodings:
MRS <Xt>, HPFAR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return HPFAR_EL2;
elsif PSTATE.EL == EL3 then
return HPFAR_EL2;
MSR HPFAR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
HPFAR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
HPFAR_EL2 = X[t];