PMCCNTR_EL0, Performance Monitors Cycle Count Register
The PMCCNTR_EL0 characteristics are:
Purpose
Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. See 'Time as measured by the Performance Monitors cycle counter' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile for more information.
PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.
Configuration
AArch64 System register PMCCNTR_EL0 bits [63:0] are architecturally mapped to AArch32 System register PMCCNTR[63:0] .
AArch64 System register PMCCNTR_EL0 bits [63:0] are architecturally mapped to External register PMCCNTR_EL0[63:0] .
All counters are subject to any changes in clock frequency, including clock stopping caused by the WFI and WFE instructions. This means that it is CONSTRAINED UNPREDICTABLE whether or not PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and WFE instructions.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
Attributes
PMCCNTR_EL0 is a 64-bit register.
Field descriptions
The PMCCNTR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CCNT | |||||||||||||||||||||||||||||||
CCNT | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCNT, bits [63:0]
Cycle count. Depending on the values of PMCR_EL0.{LC,D}, this field increments in one of the following ways:
- Every processor clock cycle.
- Every 64th processor clock cycle.
Writing 1 to PMCR_EL0.C sets this field to 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the PMCCNTR_EL0
Accesses to this register use the following encodings:
MRS <Xt>, PMCCNTR_EL0
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1101 | 0b000 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && PMUSERENR_EL0.<CR,EN> == '00' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMCCNTR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMCCNTR_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMCCNTR_EL0; elsif PSTATE.EL == EL3 then return PMCCNTR_EL0;
MSR PMCCNTR_EL0, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1101 | 0b000 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && PMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else PMCCNTR_EL0 = X[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else PMCCNTR_EL0 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else PMCCNTR_EL0 = X[t]; elsif PSTATE.EL == EL3 then PMCCNTR_EL0 = X[t];