PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
The PMINTENCLR_EL1 characteristics are:
Purpose
Disables the generation of interrupt requests on overflows from the Cycle Count Register, PMCCNTR_EL0, and the event counters PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.
Configuration
AArch64 System register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENCLR[31:0] .
AArch64 System register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to External register PMINTENCLR_EL1[31:0] .
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
Attributes
PMINTENCLR_EL1 is a 64-bit register.
Field descriptions
The PMINTENCLR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| C | P<n>, bit [n] | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
C, bit [31]
PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are:
| C | Meaning |
|---|---|
| 0b0 |
When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect. |
| 0b1 |
When read, means the cycle counter overflow interrupt request is enabled. When written, disables the cycle count overflow interrupt request. |
P<n>, bit [n], for n = 0 to 30
Event counter overflow interrupt request disable bit for PMEVCNTR<n>_EL0.
If N is less than 31, then bits [30:N] are RAZ/WI. When EL2 is implemented and enabled in the current Security state, in EL1, N is the value in MDCR_EL2.HPMN. Otherwise, N is the value in PMCR_EL0.N.
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect. |
| 0b1 |
When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, disables the PMEVCNTR<n>_EL0 interrupt request. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the PMINTENCLR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, PMINTENCLR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1110 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMINTENCLR_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMINTENCLR_EL1;
elsif PSTATE.EL == EL3 then
return PMINTENCLR_EL1;
MSR PMINTENCLR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1110 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMINTENCLR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMINTENCLR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
PMINTENCLR_EL1 = X[t];