TRCCIDCCTLR0, Context Identifier Comparator Control Register 0
The TRCCIDCCTLR0 characteristics are:
Purpose
Contains Context identifier mask values for the TRCCIDCVR<n> registers, for n = 0 to 3.
Configuration
AArch64 System register TRCCIDCCTLR0 bits [31:0] are architecturally mapped to External register TRCCIDCCTLR0[31:0] .
This register is present only when TRCIDR4.NUMCIDC > 0x0, TRCIDR2.CIDSIZE > 0b00000 and ETE is implemented. Otherwise, direct accesses to TRCCIDCCTLR0 are UNDEFINED.
Attributes
TRCCIDCCTLR0 is a 64-bit register.
Field descriptions
The TRCCIDCCTLR0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
COMP3<m>, bit [m+24] | COMP2<m>, bit [m+16] | COMP1<m>, bit [m+8] | COMP0<m>, bit [m] | ||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
COMP3<m>, bit [m+24], for m = 0 to 7
When TRCIDR4.NUMCIDC > 3:
When TRCIDR4.NUMCIDC > 3:
TRCCIDCVR3 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR3. Each bit in this field corresponds to a byte in TRCCIDCVR3.
COMP3<m> | Meaning |
---|---|
0b0 |
The trace unit includes TRCCIDCVR3[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
0b1 |
The trace unit ignores TRCCIDCVR3[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
This bit is RES0 if m >= TRCIDR2.CIDSIZE.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
COMP2<m>, bit [m+16], for m = 0 to 7
When TRCIDR4.NUMCIDC > 2:
When TRCIDR4.NUMCIDC > 2:
TRCCIDCVR2 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR2. Each bit in this field corresponds to a byte in TRCCIDCVR2.
COMP2<m> | Meaning |
---|---|
0b0 |
The trace unit includes TRCCIDCVR2[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
0b1 |
The trace unit ignores TRCCIDCVR2[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
This bit is RES0 if m >= TRCIDR2.CIDSIZE.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
COMP1<m>, bit [m+8], for m = 0 to 7
When TRCIDR4.NUMCIDC > 1:
When TRCIDR4.NUMCIDC > 1:
TRCCIDCVR1 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR1. Each bit in this field corresponds to a byte in TRCCIDCVR1.
COMP1<m> | Meaning |
---|---|
0b0 |
The trace unit includes TRCCIDCVR1[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
0b1 |
The trace unit ignores TRCCIDCVR1[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
This bit is RES0 if m >= TRCIDR2.CIDSIZE.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
COMP0<m>, bit [m], for m = 0 to 7
When TRCIDR4.NUMCIDC > 0:
When TRCIDR4.NUMCIDC > 0:
TRCCIDCVR0 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR0. Each bit in this field corresponds to a byte in TRCCIDCVR0.
COMP0<m> | Meaning |
---|---|
0b0 |
The trace unit includes TRCCIDCVR0[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
0b1 |
The trace unit ignores TRCCIDCVR0[(m×8+7):(m×8)] when it performs the Context identifier comparison. |
This bit is RES0 if m >= TRCIDR2.CIDSIZE.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Accessing the TRCCIDCCTLR0
If software uses the TRCCIDCVR<n> registers, for n = 0 to 3, then it must program this register.
If software sets a mask bit to 0b1 then it must program the relevant byte in TRCCIDCVR<n> to 0x00.
If any bit is 0b1 and the relevant byte in TRCCIDCVR<n> is not 0x00, the behavior of the Context Identifier Comparator is CONSTRAINED UNPREDICTABLE. In this scenario the comparator might match unexpectedly or might not match.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Accesses to this register use the following encodings:
MRS <Xt>, TRCCIDCCTLR0
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0011 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCCIDCCTLR0; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCCIDCCTLR0; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCCIDCCTLR0;
MSR TRCCIDCCTLR0, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0011 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCCIDCCTLR0 = X[t]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCCIDCCTLR0 = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCCIDCCTLR0 = X[t];