TRCIDR3, ID Register 3

The TRCIDR3 characteristics are:

Purpose

Returns the base architecture of the trace unit.

Configuration

AArch64 System register TRCIDR3 bits [31:0] are architecturally mapped to External register TRCIDR3[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR3 are UNDEFINED.

Attributes

TRCIDR3 is a 64-bit register.

Field descriptions

The TRCIDR3 bit assignments are:

Bits [63:32]

Reserved, RES0.

NOOVERFLOW, bit [31]

Indicates if overflow prevention is implemented.

NUMPROC[2:0], bits [30:28]

This field is bits[2:0] of NUMPROC[4:0].

Indicates the number of PEs available for tracing.

This field reads as 0b00000.

The NUMPROC field is split as follows:

• NUMPROC[2:0] is TRCIDR3[30:28].
• NUMPROC[4:3] is TRCIDR3[13:12].

SYSSTALL, bit [27]

When TRCIDR3.STALLCTL == 0b1:

Indicates if stalling of the PE is permitted.

The value of this field might be dynamic and change based on system conditions.

Otherwise:

Reserved, RES0.

STALLCTL, bit [26]

Indicates if trace unit implements stalling of the PE.

SYNCPR, bit [25]

Indicates if an implementation has a fixed synchronization period.

This bit reads as 0b0.

TRCERR, bit [24]

Indicates forced tracing of System Error exceptions is implemented.

This bit reads as 0b1.

Bit [23]

Reserved, RES0.

EXLEVEL_NS_EL2, bit [22]

Indicates if Non-secure EL2 implemented.

EXLEVEL_NS_EL1, bit [21]

Indicates if Non-secure EL1 implemented.

EXLEVEL_NS_EL0, bit [20]

Indicates if Non-secure EL0 implemented.

EXLEVEL_S_EL3, bit [19]

Indicates if Secure EL3 implemented.

EXLEVEL_S_EL2, bit [18]

Indicates if Secure EL2 implemented.

EXLEVEL_S_EL1, bit [17]

Indicates if Secure EL1 implemented.

EXLEVEL_S_EL0, bit [16]

Indicates if Secure EL0 implemented.

Bits [15:14]

Reserved, RES0.

NUMPROC[4:3], bits [13:12]

This field is bits[4:3] of NUMPROC[4:0].

See NUMPROC[2:0] for the field description.

CCITMIN, bits [11:0]

When TRCIDR0.TRCCCI == 0b1:

Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.

When cycle counting in the instruction trace is supported, that is TRCIDR0.TRCCCI == 0b1, then the minimum value of this field is 0x001.

Otherwise:

Reserved, RES0.

if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR3;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR3;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR3;