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TRCIDR5, ID Register 5

The TRCIDR5 characteristics are:

Purpose

Returns the tracing capabilities of the trace unit.

Configuration

AArch64 System register TRCIDR5 bits [31:0] are architecturally mapped to External register TRCIDR5[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR5 are UNDEFINED.

Attributes

TRCIDR5 is a 64-bit register.

Field descriptions

The TRCIDR5 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0NUMCNTRNUMSEQSTATERES0LPOVERRIDEATBTRIGTRACEIDSIZERES0NUMEXTINSELNUMEXTIN
313029282726252423222120191817161514131211109876543210

Bits [63:31]

Reserved, RES0.

NUMCNTR, bits [30:28]

Indicates the number of counters that are available for tracing.

NUMCNTRMeaning
0b000

No counters are available.

0b001

One counter implemented.

0b010

Two counters implemented.

0b011

Three counters implemented.

0b100

Four counters implemented.

All other values are reserved.

This field is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

NUMSEQSTATE, bits [27:25]

Indicates if the sequencer is implemented and the number of sequencer states that are implemented.

NUMSEQSTATEMeaning
0b000

The sequencer is not implemented.

0b100

Four sequencer states are implemented.

All other values are reserved.

This field is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

Bit [24]

Reserved, RES0.

LPOVERRIDE, bit [23]

Indicates support for Low-power Override Mode.

LPOVERRIDEMeaning
0b0

The trace unit does not support Low-power Override Mode.

0b1

The trace unit support Low-power Override Mode.

ATBTRIG, bit [22]

Indicates if the implementation can support ATB triggers.

ATBTRIGMeaning
0b0

The implementation does not support ATB triggers.

0b1

The implementation supports ATB triggers.

This bit is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

TRACEIDSIZE, bits [21:16]

Indicates the trace ID width.

TRACEIDSIZEMeaning
0b000000

The external trace interface is not implemented.

0b000111

The implementation supports a 7-bit trace ID.

All other values are reserved.

Note that AMBA ATB requires a 7-bit trace ID width.

Bits [15:12]

Reserved, RES0.

NUMEXTINSEL, bits [11:9]

Indicates how many external input selector resources are implemented.

NUMEXTINSELMeaning
0b000

No external input selector resources are available.

0b001

1 external input selector resource is available.

0b010

2 external input selector resources are available.

0b011

3 external input selector resources are available.

0b100

4 external input selector resources are available.

All other values are reserved.

NUMEXTIN, bits [8:0]

Indicates how many external inputs are implemented.

NUMEXTINMeaning
0b111111111

Unified PMU event selection.

All other values are reserved.

Accessing the TRCIDR5

Accesses to this register use the following encodings:

MRS <Xt>, TRCIDR5

op0op1CRnCRmop2
0b100b0010b00000b11010b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR5;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR5;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR5;
              


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