TRCSSCCR<n>, Single-shot Comparator Control Register <n>, n = 0 - 7
The TRCSSCCR<n> characteristics are:
Purpose
Controls the corresponding Single-shot Comparator Control resource.
Configuration
AArch64 System register TRCSSCCR<n> bits [31:0] are architecturally mapped to External register TRCSSCCR<n>[31:0] .
This register is present only when TRCIDR4.NUMSSCC > n and ETE is implemented. Otherwise, direct accesses to TRCSSCCR<n> are UNDEFINED.
Attributes
TRCSSCCR<n> is a 64-bit register.
Field descriptions
The TRCSSCCR<n> bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RST | ARC<m>, bit [m+16] | SAC<m>, bit [m] | ||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:25]
Reserved, RES0.
RST, bit [24]
Selects the Single-shot Comparator Control mode.
RST | Meaning |
---|---|
0b0 |
The Single-shot Comparator Control is in single-shot mode. |
0b1 |
The Single-shot Comparator Control is in multi-shot mode. |
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
ARC<m>, bit [m+16], for m = 0 to 7
Selects one or more Address Range Comparators for Single-shot control.
ARC<m> | Meaning |
---|---|
0b0 |
The Address Range Comparator m, is not selected for Single-shot control. |
0b1 |
The Address Range Comparator m, is selected for Single-shot control. |
This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
SAC<m>, bit [m], for m = 0 to 15
Selects one or more Single Address Comparators for Single-shot control.
SAC<m> | Meaning |
---|---|
0b0 |
The Single Address Comparator m, is not selected for Single-shot control. |
0b1 |
The Single Address Comparator m, is selected for Single-shot control. |
This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Accessing the TRCSSCCR<n>
Must be programmed if any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 0b1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Accesses to this register use the following encodings:
MRS <Xt>, TRCSSCCR<n>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0001 | 0b0[n:2:0] | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCCR[UInt(CRm<2:0>)]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCCR[UInt(CRm<2:0>)]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCCR[UInt(CRm<2:0>)];
MSR TRCSSCCR<n>, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0001 | 0b0[n:2:0] | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCCR[UInt(CRm<2:0>)] = X[t]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCCR[UInt(CRm<2:0>)] = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCCR[UInt(CRm<2:0>)] = X[t];