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TRCSTATR, Trace Status Register

The TRCSTATR characteristics are:

Purpose

Returns the trace unit status.

Configuration

AArch64 System register TRCSTATR bits [31:0] are architecturally mapped to External register TRCSTATR[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSTATR are UNDEFINED.

Attributes

TRCSTATR is a 64-bit register.

Field descriptions

The TRCSTATR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PMSTABLEIDLE
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

PMSTABLE, bit [1]

Programmers' model stable bit.

PMSTABLEMeaning
0b0

The programmers' model is not stable.

0b1

The programmers' model is stable.

This bit is UNKNOWN while the trace unit is enabled.

IDLE, bit [0]

Idle Status bit.

IDLEMeaning
0b0

The trace unit is not idle.

0b1

The trace unit is idle.

Accessing the TRCSTATR

Accesses to this register use the following encodings:

MRS <Xt>, TRCSTATR

op0op1CRnCRmop2
0b100b0010b00000b00110b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSTATR;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSTATR;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSTATR;
              


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