AMDEVARCH, Activity Monitors Device Architecture Register
The AMDEVARCH characteristics are:
Identifies the programmers' model architecture of the AMU component.
The power domain of AMDEVARCH is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMDEVARCH are RES0.
AMDEVARCH is a 32-bit register.
The AMDEVARCH bit assignments are:
ARCHITECT, bits [31:21]
Defines the architecture of the component. For AMU, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
PRESENT, bit 
When set to 1, indicates that the DEVARCH is present.
This field is 1 in Armv8.
REVISION, bits [19:16]
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
Architecture revision is AMUv1.
All other values are reserved.
ARCHID, bits [15:0]
Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.
- Bits [15:12] are the architecture version, 0x0.
- Bits [11:0] are the architecture part number, 0xA66.
This corresponds to AMU architecture version AMUv1.
Accessing the AMDEVARCH
AMDEVARCH can be accessed through the memory-mapped interfaces:
Access on this interface is RO.