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EDPRSR, External Debug Processor Status Register

The EDPRSR characteristics are:

Purpose

Holds information about the reset and powerdown state of the PE.

Configuration

EDPRSR contains fields that are in the Core power domain and fields that are in the Debug power domain.

Some of the fields in the Core power domain are in the Cold reset domain and others are in the Warm reset domain. See the field descriptions for more information. However:

  • Fields that are in the Cold reset domain are not affected by a warm reset and are not affected by an External debug reset.

  • Fields in the Warm reset domain are also reset by a Cold reset but are not affected by an External debug reset.

  • Fields in the Debug power domain are not affected by a Warm reset and are not affected by a Cold reset.

If ARMv8.3-DoPD is implemented then all fields in this register are in the Core power domain.

Attributes

EDPRSR is a 32-bit register.

Field descriptions

The EDPRSR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0STADETADSDRSPMADEPMADSDADEDADDLKOSLKHALTEDSRRSPDPU

Bits [31:14]

Reserved, RES0.

STAD, bit [13]

When TRBE is implemented:

Sticky ETAD error. Set to 1 when a Non-secure external debug interface access to an external PE Trace Unit register returns an error because AllowExternalTraceAccess() == FALSE for the access.

STADMeaning
0b0

No Non-secure external debug interface accesses to the PE Trace Unit registers have failed because AllowExternalTraceAccess() == FALSE for the access since EDPRSR was last read.

0b1

At least one Non-secure external debug interface access to the PE Trace Unit registers has failed and returned an error because AllowExternalTraceAccess() == FALSE for the access since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE then this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE then it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This bit is in the Core power domain.

On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

Reserved, RES0.

ETAD, bit [12]

When TRBE is implemented:

External Trace Access Disable status.

ETADMeaning
0b0

External Non-secure PE Trace Unit accesses enabled. AllowExternalTraceAccess() == TRUE.

0b1

External Non-secure PE Trace Unit accesses disabled. AllowExternalTraceAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

Reserved, RES0.

SDR, bit [11]

Sticky debug restart. Set to 1 when the PE exits Debug state.

Permitted values are:

SDRMeaning
0b0

The PE has not restarted since EDPRSR was last read.

0b1

The PE has restarted since EDPRSR was last read.

Note

If a reset occurs when the PE is in Debug state, the PE exits Debug state. SDR is UNKNOWN on Warm reset, meaning a debugger must also use the SR bit to determine whether the PE has left Debug state.

If The Core power domain is powered up, then following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain and the Warm reset domain.

This field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • When SoftwareLockStatus(), access to this field is RO.
  • Otherwise, access to this field is RC.

SPMAD, bit [10]

When ARMv8.4-Debug is implemented:

Sticky EPMAD error. Set to 1 if an external debug interface access to a Performance Monitors register returns an error because AllowExternalPMUAccess() == FALSE.

Permitted values are:

SPMADMeaning
0b0

No Non-secure external debug interface accesses to the external Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read..

0b1

At least one Non-secure external debug interface access to the external Performance Monitors register has failed and returned an error because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented, and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • When SoftwareLockStatus(), access to this field is RO.
  • Otherwise, access to this field is RC.


Otherwise:

Sticky EPMAD error.

SPMADMeaning
0b0

No external debug interface accesses to the Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.

0b1

At least one external debug interface access to the Performance Monitors registers has failed and returned an error because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented, and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or OSLockStatus(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • When SoftwareLockStatus(), access to this field is RO.
  • Otherwise, access to this field is RC.

EPMAD, bit [9]

When ARMv8.4-Debug is implemented:

External Performance Monitors Access Disable status.

EPMADMeaning
0b0

External Non-secure Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE.

0b1

External Non-secure Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

External Performance Monitors access disable status.

EPMADMeaning
0b0

External Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE.

0b1

External Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or OSLockStatus(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

SDAD, bit [8]

When ARMv8.4-Debug is implemented:

Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.

SDADMeaning
0b0

No Non-secure external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.

0b1

At least one Non-secure external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.

SDADMeaning
0b0

No external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.

0b1

At least one external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This bit is UNKNOWN on reads if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

EDAD, bit [7]

When ARMv8.4-Debug is implemented:

External debug access disable status.

EDADMeaning
0b0

External Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE.

0b1

External Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 disabled. AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


When ARMv8.2-Debug is implemented:

External debug access disable status.

EDADMeaning
0b0

External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE.

0b1

External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 disabled. AllowExternalDebugAccess() == FALSE.

This bit is not valid and reads UNKNOWN if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

External debug access disable status.

EDADMeaning
0b0

External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE.

0b1

External access to breakpoint registers, watchpoint registers disabled. It is IMPLEMENTATION DEFINED whether accesses to OSLAR_EL1 are enabled or disabled. AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), or DoubleLockStatus() or EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

DLK, bit [6]

When ARMv8.4-Debug is implemented:

This field is RES0.


When ARMv8.2-Debug is implemented and ARMv8.0-DoubleLock is implemented:

From Armv8.2, this field is deprecated.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When IsCorePowered() and !DoubleLockStatus(), access to this field is RAZ.
  • Otherwise, access to this field is UNKNOWN.


When ARMv8.0-DoubleLock is implemented:

This field returns the result of the pseudocode function DoubleLockStatus().

If the Core power domain is powered up and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether:

  • EDPRSR.PU reads as 1, EDPRSR.DLK reads as 1, and EDPRSR.SPD is UNKNOWN.
  • EDPRSR.PU reads as 0, EDPRSR.DLK is UNKNOWN, and EDPRSR.SPD reads as 0.

This field is in the Core power domain.

DLKMeaning
0b0

DoubleLockStatus() returns FALSE.

0b1

DoubleLockStatus() returns TRUE and the Core power domain is powered up.

Accessing this field has the following behavior:

  • When !IsCorePowered(), access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.


Otherwise:

Reserved, RES0.

OSLK, bit [5]

OS lock status bit.

A read of this bit returns the value of OSLSR_EL1.OSLK.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), DoubleLockStatus() and EDPRSR.R == 1, access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

HALTED, bit [4]

Halted status bit.

HALTEDMeaning
0b0

PE is in Non-debug state.

0b1

PE is in Debug state.

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered(), access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

SR, bit [3]

Sticky core reset status bit.

Permitted values are:

SRMeaning
0b0

The non-debug logic of the PE is not in reset state and has not been reset since the last time EDPRSR was read.

0b1

The non-debug logic of the PE is in reset state or has been reset since the last time EDPRSR was read.

If EDPRSR.PU reads as 1 and EDPRSR.R reads as 0, which means that the Core power domain is in a powerup state and that the non-debug logic of the PE is not in reset state, then following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, it is UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain and the Warm reset domain.

This field resets to 1.

Accessing this field has the following behavior:

  • When !IsCorePowered() or DoubleLockStatus(), access to this field is UNKNOWN.
  • When SoftwareLockStatus(), access to this field is RO.
  • Otherwise, access to this field is RC.

R, bit [2]

PE reset status bit.

Permitted values are:

RMeaning
0b0

The non-debug logic of the PE is not in reset state.

0b1

The non-debug logic of the PE is in reset state.

If ARMv8.0-DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)

This field is in the Core power domain.

Accessing this field has the following behavior:

  • When !IsCorePowered() or DoubleLockStatus(), access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

SPD, bit [1]

Sticky Core powerdown status bit.

SPDMeaning
0b0

If EDPRSR.PU is 0, it is not known whether the state of the debug registers in the Core power domain is lost.

If EDPRSR.PU is 1, the state of the debug registers in the Core power domain has not been lost.

0b1

The state of the debug registers in the Core power domain has been lost.

If the Core power domain is powered up, then, following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
  • If ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

When the value of EDPRSR.PU is 0 indicating that the Core power domain is in either retention or powerdown state, EDPRSR.SPD reads as 0. For more information, see 'EDPRSR.SPD when the Core domain is in either retention or powerdown state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support).

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support).

This field is in the Core power domain and the Cold reset domain.

On a Cold reset, this field resets to 1.

Accessing this field has the following behavior:

  • When !IsCorePowered(), access to this field is RAZ.
  • When IsCorePowered() and DoubleLockStatus(), access to this field is UNKNOWN.
  • Otherwise, access to this field is RO.

PU, bit [0]

When ARMv8.3-DoPD is implemented:

Core powerup status bit.

Access to this field is RAO.


When ARMv8.2-Debug is implemented:

Core powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.

PUMeaning
0b0

Either the Core power domain is in a low-power or powerdown state, or ARMv8.0-DoubleLock is implemented and DoubleLockStatus() == TRUE, meaning the debug registers in the Core power domain cannot be accessed.

0b1

The Core power domain is in a powerup state, and either ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE, meaning the debug registers in the Core power domain can be accessed.

If ARMv8.0-DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)

Access to this field is RO.


Otherwise:

Core powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.

When the Core power domain is powered-up and DoubleLockStatus() == TRUE, then the value of EDPRSR.PU is IMPLEMENTATION DEFINED. See the description of the DLK bit for more information.

Otherwise, permitted values are:

PUMeaning
0b0

Core power domain is in a low-power or powerdown state where the debug registers in the Core power domain cannot be accessed.

0b1

Core power domain is in a powerup state where the debug registers in the Core power domain can be accessed.

If ARMv8.0-DoubleLock is implemented, the Core power domain is powered up, and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether this bit reads as 0 or 1.

If ARMv8.0-DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)

Access to this field is RO.

Accessing the EDPRSR

On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.

If the Core power domain is powered up (EDPRSR.PU == 1), then following a read of EDPRSR:

  • If ARMv8.0-DoubleLock is not implemented or DoubleLockStatus() == FALSE, then:
    • EDPRSR.{SDR, SPMAD, SDAD, SPD} are cleared to 0.
    • EDPRSR.SR is cleared to 0 if the non-debug logic of the PE is not in reset state (EDPRSR.R == 0).
  • Otherwise it is CONSTRAINED UNPREDICTABLE whether or not this clearing occurs.

If the Core power domain is powered down (EDPRSR.PU == 0), then:

  • EDPRSR.{SDR, SPMAD, SDAD, SR} are all UNKNOWN, and are either reset or restored on being powered up.
  • EDPRSR.SPD is not cleared following a read of EDPRSR. See the SPD bit description for more information.

The clearing of bits is an indirect write to EDPRSR.

EDPRSR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x314EDPRSR

This interface is accessible as follows:

  • When ARMv8.3-DoPD is not implemented or IsCorePowered() access to this register is RO.
  • Otherwise access to this register returns an Error.


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