GICD_ICFGR<n>E, Interrupt Configuration Registers (Extended SPI Range), n = 0 - 63
The GICD_ICFGR<n>E characteristics are:
Purpose
Determines whether the corresponding SPI in the extended SPI range is edge-triggered or level-sensitive.
Configuration
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when GIC, >=3.1 is implemented. Otherwise, direct accesses to GICD_ICFGR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ICFGR<n>E registers is ((GICD_TYPER.ESPI_range+1)*2). Registers are numbered from 0.
Attributes
GICD_ICFGR<n>E is a 32-bit register.
Field descriptions
The GICD_ICFGR<n>E bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Int_config<x>, bits [2x+1:2x], for x = 0 to 15 |
Int_config<x>, bits [2x+1:2x], for x = 0 to 15
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit[2x]) is RES0.
Possible values of Int_config[1] (bit[2x+1]) are:
Int_config<x> | Meaning |
---|---|
0b00 |
Corresponding interrupt is level-sensitive. |
0b01 |
Corresponding interrupt is edge-triggered. |
This field resets to an architecturally UNKNOWN value.
Accessing the GICD_ICFGR<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICD_ICFGR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICD_ICFGR<n>E can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x1E00 + 4n | GICD_ICFGR<n>E |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.