GICD_ICPENDR<n>, Interrupt Clear-Pending Registers, n = 0 - 31
The GICD_ICPENDR<n> characteristics are:
Removes the pending state from the corresponding interrupt.
Some or all RW fields of this register have defined reset values.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
GICD_ICPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
GICD_ICPENDR<n> is a 32-bit register.
The GICD_ICPENDR<n> bit assignments are:
|Clear_pending_bit<x>, bit [x], for x = 0 to 31|
Clear_pending_bit<x>, bit [x], for x = 0 to 31
For SPIs and PPIs, removes the pending state from interrupt number 32n + x. Reads and writes have the following behavior:
If read, indicates that the corresponding interrupt is not pending on any PE.
If written, has no effect.
If read, indicates that the corresponding interrupt is pending, or active and pending:
If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_ICPENDR<n> number, n, is given by n = m DIV 32.
- The offset of the required GICD_ICPENDR is (0x200 + (4*n)).
- The bit number of the required group modifier bit in this register is m MOD 32.
Accessing the GICD_ICPENDR<n>
Clear-pending bits for SGIs are RO/WI.
When affinity routing is enabled for the Security state of an interrupt:
- Bits corresponding to SGIs and PPIs are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ICPENDR0.
- Bits corresponding to Group 0 and Group 1 Secure interrupts can only be cleared by Secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.
GICD_ICPENDR<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0280 + 4n||GICD_ICPENDR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.