GICD_NSACR<n>, Non-secure Access Control Registers, n = 0 - 63
The GICD_NSACR<n> characteristics are:
Enables Secure software to permit Non-secure software on a particular PE to create and control Group 0 interrupts.
Some or all RW fields of this register have defined reset values.
The concept of selective enabling of Non-secure access to Group 0 and Secure Group 1 interrupts applies to SGIs and SPIs.
GICD_NSACR0 is a Banked register used for SGIs. A copy is provided for every PE that has a CPU interface and that supports this feature.
GICD_NSACR<n> is a 32-bit register.
The GICD_NSACR<n> bit assignments are:
|NS_access<x>, bits [2x+1:2x], for x = 0 to 15|
NS_access<x>, bits [2x+1:2x], for x = 0 to 15
Controls Non-secure access of the interrupt with ID 16n + x.
If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI.
Otherwise, the field is RW and determines the level of Non-secure control permitted if the interrupt is a Secure interrupt. If the interrupt is a Non-secure interrupt, this field is ignored.
The possible values of each 2-bit field are:
No Non-secure access is permitted to fields associated with the corresponding interrupt.
Non-secure read and write access is permitted to set-pending bits in GICD_ISPENDR<n> associated with the corresponding interrupt. A Non-secure write access to GICD_SETSPI_NSR is permitted to set the pending state of the corresponding interrupt. A Non-secure write access to GICD_SGIR is permitted to generate a Secure SGI for the corresponding interrupt.
An implementation might also provide read access to clear-pending bits in GICD_ICPENDR<n> associated with the corresponding interrupt.
As 0b01, but adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDR<n> registers. A Non-secure write access to GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding interrupt. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVER<n> and GICD_ICACTIVER<n> registers.
For GICD_NSACR0 this encoding is reserved and treated as 10.
For all other GICD_NSACR<n> registers this encoding is treated as 0b10, but adds Non-secure read and write access permission to GICD_ITARGETSR<n> and GICD_IROUTER<n> fields associated with the corresponding interrupt.
This field resets to 0.
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_NSACR<n> number, n, is given by n = m DIV 16.
- The offset of the required GICD_NSACR<n> register is (0xE00 + (4*n)).
Because each field in this register comprises two bits, GICD_NSACR0 controls access rights to SGI registers, GICD_NSACR1 controls access to PPI registers (and is always RAZ/WI), and all other GICD_NSACR<n> registers control access to SPI registers.
For compatibility with GICv2, writes to GICD_NSACR0 for a particular PE must be coordinated within the Distributor and must update GICR_NSACR for the Redistributor associated with that PE.
Accessing the GICD_NSACR<n>
When GICD_CTLR.DS==1, this register is RAZ/WI.
These registers are Secure, and are RAZ/WI to Non-secure accesses.
These registers are always used when affinity routing is not enabled. When affinity routing is enabled for the Secure state, GICD_NSACR0 is RES0 and GICR_NSACR provides equivalent functionality for SGIs.
These registers do not support PPIs, therefore GICD_NSACR1 is RAZ/WI.
GICD_NSACR<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0E00 + 4n||GICD_NSACR<n>|
When When IsAccessSecure() access on this interface is RW.