GICR_WAKER, Redistributor Wake Register
The GICR_WAKER characteristics are:
Purpose
Permits software to control the behavior of the WakeRequest power management signal corresponding to the Redistributor. Power management operations follow the rules in Power management.
Configuration
Some or all RW fields of this register have defined reset values.
A copy of this register is provided for each Redistributor.
Attributes
GICR_WAKER is a 32-bit register.
Field descriptions
The GICR_WAKER bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | RES0 | ChildrenAsleep | ProcessorSleep | IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||
IMPLEMENTATION DEFINED, bit [31]
IMPLEMENTATION DEFINED.
Bits [30:3]
Reserved, RES0.
ChildrenAsleep, bit [2]
Read-only. Indicates whether the connected PE is quiescent:
| ChildrenAsleep | Meaning |
|---|---|
| 0b0 |
An interface to the connected PE might be active. |
| 0b1 |
All interfaces to the connected PE are quiescent. |
This field resets to 1.
ProcessorSleep, bit [1]
Indicates whether the Redistributor can assert the WakeRequest signal:
| ProcessorSleep | Meaning |
|---|---|
| 0b0 |
This PE is not in, and is not entering, a low power state. |
| 0b1 |
The PE is either in, or is in the process of entering, a low power state. All interrupts that arrive at the Redistributor:
Note When ProcessorSleep == 1, the Redistributor must ensure that any interrupts that are pending on the CPU interface are released. For an implementation that is using the GIC Stream Protocol Interface:
|
Before powering down a PE, software must set this bit to 1 and wait until ChildrenAsleep == 1. After powering up a PE, or following a failed powerdown, software must set this bit to 0 and wait until ChildrenAsleep == 0.
Changing ProcessorSleep from 1 to 0 when ChildrenAsleep is not 1 results in UNPREDICTABLE behavior.
Changing ProcessorSleep from 0 to 1 when the Enable for each interrupt group in the associated CPU interface is not 0 results in UNPREDICTABLE behavior.
This field resets to 1.
IMPLEMENTATION DEFINED, bit [0]
IMPLEMENTATION DEFINED.
Accessing the GICR_WAKER
When GICD_CTLR.DS==1, this register is always accessible.
When GICD_CTLR.DS==0, this is a Secure register. This register is RAZ/WI to Non-secure accesses.
To ensure a Redistributor is quiescent, software must write to GICR_WAKER with ProcessorSleep == 1, then poll the register until ChildrenAsleep == 1.
Resetting the connected PE when GICR_WAKER.ProcessorSleep==0 or GICR_WAKER.ChildresAsleep==0, can lead to UNPREDICTABLE behaviour in the IRI.
Resetting the IRI when GICR_WAKER.ProcessorSleep==0 or GICR_WAKER.ChildresAsleep==0 can lead to UNPREDICTABLE behaviour in the connected PE.
GICR_WAKER can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x0014 | GICR_WAKER |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.