PMLAR, Performance Monitors Lock Access Register
The PMLAR characteristics are:
Allows or disallows access to the Performance Monitors registers through a memory-mapped interface.
It is IMPLEMENTATION DEFINED whether PMLAR is implemented in the Core power domain or in the Debug power domain.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
PMLAR ignores writes if the Software Lock is not implemented and ignores writes for other accesses to the external debug interface.
The Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage.
Software uses PMLAR to set or clear the lock, and PMLSR to check the current status of the lock.
PMLAR is a 32-bit register.
The PMLAR bit assignments are:
KEY, bits [31:0]
Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock, enabling write accesses to this component's registers through a memory-mapped interface.
Writing any other value to this register locks the lock, disabling write accesses to this component's registers through a memory mapped interface.
Accessing the PMLAR
PMLAR can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When ARMv8.3-DoPD is not implemented or IsCorePowered() access to this register is WO.
- Otherwise access to this register returns an Error.