You copied the Doc URL to your clipboard.

TRCCNTVR<n>, Counter Value Register <n>, n = 0 - 3

The TRCCNTVR<n> characteristics are:

Purpose

This sets or returns the value of counter <n>.

Configuration

External register TRCCNTVR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCCNTVR<n>[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR5.NUMCNTR > n and ETE is implemented. Otherwise, direct accesses to TRCCNTVR<n> are RES0.

Attributes

TRCCNTVR<n> is a 32-bit register.

Field descriptions

The TRCCNTVR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0VALUE

Bits [31:16]

Reserved, RES0.

VALUE, bits [15:0]

Contains the count value of counter.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCCNTVR<n>

Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.COUNTERS[n] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

TRCCNTVR<n> can be accessed through the external debug interface:

ComponentOffset
ETE0x160 + 4n

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


Was this page helpful? Yes No