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TRCEVENTCTL1R, Event Control 1 Register

The TRCEVENTCTL1R characteristics are:

Purpose

Controls the behavior of the ETEEvents that TRCEVENTCTL0R selects.

Configuration

External register TRCEVENTCTL1R bits [31:0] are architecturally mapped to AArch64 System register TRCEVENTCTL1R[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCEVENTCTL1R are RES0.

Attributes

TRCEVENTCTL1R is a 32-bit register.

Field descriptions

The TRCEVENTCTL1R bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0LPOVERRIDEATBRES0INSTEN<m>, bit [m]

Bits [31:13]

Reserved, RES0.

LPOVERRIDE, bit [12]

When TRCIDR5.LPOVERRIDE == 0b1:

Low-power Override Mode select.

LPOVERRIDEMeaning
0b0

Trace unit Low-power Override Mode is not enabled. That is, the trace unit is permitted to enter low-power state.

0b1

Trace unit Low-power Override Mode is enabled. That is, entry to a low-power state does not affect the trace unit resources or trace generation.


Otherwise:

Reserved, RES0.

ATB, bit [11]

When TRCIDR5.ATBTRIG == 0b1:

AMBA Trace Bus (ATB) trigger enable.

If a CoreSight ATB interface is implemented then when ETEEvent 0 occurs the trace unit sets:

If the width of ATDATA is greater than the width of TRCTRACEIDR.TRACEID then the trace unit zeros the upper ATDATA bits.

If ETEEvent 0 is programmed to occur based on program execution, such as an address comparator, the ATB trigger might not be inserted into the ATB stream at the same time as any trace generated by that program execution is output by the trace unit. Typically, the generated trace might be buffered in a trace unit which means that the ATB trigger would be output before the associated trace is output.

If ETEEvent 0 is asserted multiple times in close succession, the trace unit is required to generate an ATB trigger for the first assertion, but might ignore one or more of the subsequent assertions. Arm recommends that the window in which ETEEvent 0 is ignored is limited only by the time taken to output an ATB trigger.

ATBMeaning
0b0

ATB trigger is disabled.

0b1

ATB trigger is enabled.


Otherwise:

Reserved, RES0.

Bits [10:4]

Reserved, RES0.

INSTEN<m>, bit [m], for m = 0 to 3

Event element control.

INSTEN<m>Meaning
0b0

The trace unit does not generate an Event element m.

0b1

The trace unit generates an Event element m.

This bit is RES0 if m >= the number indicated by TRCIDR0.NUMEVENT.

Accessing the TRCEVENTCTL1R

Must be programmed.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCEVENTCTL1R can be accessed through the external debug interface:

ComponentOffset
ETE0x024

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


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