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TRCIDR1, ID Register 1

The TRCIDR1 characteristics are:

Purpose

Returns the tracing capabilities of the trace unit.

Configuration

External register TRCIDR1 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR1[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR1 are RES0.

Attributes

TRCIDR1 is a 32-bit register.

Field descriptions

The TRCIDR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
DESIGNERRES0RES1TRCARCHMAJTRCARCHMINREVISION

DESIGNER, bits [31:24]

Indicates which company designed the trace unit.

DESIGNERMeaning
0x41

Arm Limited.

All other values are reserved.

Bits [23:16]

Reserved, RES0.

Bits [15:12]

Reserved, RES1.

TRCARCHMAJ, bits [11:8]

Major architecture version.

TRCARCHMAJMeaning
0b1111

If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH.

All other values are reserved.

This field reads as 0b1111.

TRCARCHMIN, bits [7:4]

Minor architecture version.

TRCARCHMINMeaning
0b1111

If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH.

All other values are reserved.

This field reads as 0b1111.

REVISION, bits [3:0]

Implementation revision.

Returns an IMPLEMENTATION DEFINED value that identifies the revision of:

  • The trace registers.
  • The OS Lock registers.

Arm recommends that the initial implementation sets REVISION == 0x0 and the field then increments for any subsequent implementations. However, it is acceptable to omit some values or use another scheme to identify the revision number.

Arm recommends that TRCPIDR2.REVISION == TRCIDR1.REVISION. However, in situations where it is difficult to align these fields, such as with a metal layer fix then it is acceptable to change the REVISION fields independently.

Accessing the TRCIDR1

TRCIDR1 can be accessed through the external debug interface:

ComponentOffset
ETE0x1E4

This interface is accessible as follows:

  • When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RO.


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