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TRCPIDR0, Peripheral Identification Register 0

The TRCPIDR0 characteristics are:

Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR0 are RES0.

There are no configuration notes.

Attributes

TRCPIDR0 is a 32-bit register.

Field descriptions

The TRCPIDR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0PART_0

Bits [31:8]

Reserved, RES0.

PART_0, bits [7:0]

IMPLEMENTATION DEFINED.

Part number, bits [7:0].

The part number is selected by the designer of the component, and is stored in TRCPIDR1.PART_1 and TRCPIDR0.PART_0.

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the TRCPIDR0

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR0 can be accessed through the external debug interface:

ComponentOffset
ETE0xFE0

This interface is accessible as follows:

  • When !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RO.


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