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TRCPIDR5, Peripheral Identification Register 5

The TRCPIDR5 characteristics are:

Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR5 are RES0.

There are no configuration notes.

Attributes

TRCPIDR5 is a 32-bit register.

Field descriptions

The TRCPIDR5 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0

Bits [31:0]

Reserved, RES0.

Accessing the TRCPIDR5

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR5 can be accessed through the external debug interface:

ComponentOffset
ETE0xFD4

This interface is accessible as follows:

  • When !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RO.


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