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TRCQCTLR, Q Element Control Register

The TRCQCTLR characteristics are:

Purpose

Controls when Q elements are enabled.

Configuration

External register TRCQCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCQCTLR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR0.QFILT == 0b1 and ETE is implemented. Otherwise, direct accesses to TRCQCTLR are RES0.

Attributes

TRCQCTLR is a 32-bit register.

Field descriptions

The TRCQCTLR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0MODERANGE<m>, bit [m]

Bits [31:9]

Reserved, RES0.

MODE, bit [8]

Selects whether the Address Range Comparators selected by the RANGE field indicate address ranges where the trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to generate Q elements:

MODEMeaning
0b0

Exclude mode.

The Address Range Comparators selected by the RANGE field indicate address ranges where the trace unit must not generate Q elements. If no ranges are selected, Q elements are permitted across the entire memory map.

0b1

Include Mode.

The Address Range Comparators selected by the RANGE field indicate address ranges where the trace unit can generate Q elements. If all the implemented bits in RANGE are set to 0b0 then Q elements are disabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

RANGE<m>, bit [m], for m = 0 to 7

Specifies the Address Range Comparators to be used for controlling Q elements.

RANGE<m>Meaning
0b0

The address range that Address Range Comparator m defines, is not selected.

0b1

The address range that Address Range Comparator m defines, is selected.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCQCTLR

Must be programmed if TRCCONFIGR.QE != 0b00.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCQCTLR can be accessed through the external debug interface:

ComponentOffset
ETE0x044

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


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