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TRCSSPCICR<n>, Single-shot Processing Element Comparator Input Control Register <n>, n = 0 - 7

The TRCSSPCICR<n> characteristics are:

Purpose

Returns the status of the corresponding Single-shot Comparator Control.

Configuration

External register TRCSSPCICR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSPCICR<n>[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMSSCC > n, TRCIDR4.NUMPC > 0b0000, TRCSSCSR<n>.PC == 0b1 and ETE is implemented. Otherwise, direct accesses to TRCSSPCICR<n> are RES0.

Attributes

TRCSSPCICR<n> is a 32-bit register.

Field descriptions

The TRCSSPCICR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0PC<m>, bit [m]

Bits [31:8]

Reserved, RES0.

PC<m>, bit [m], for m = 0 to 7

Selects one or more PE Comparator Inputs for Single-shot control.

PC<m>Meaning
0b0

The single PE Comparator Input m, is not selected as for Single-shot control.

0b1

The single PE Comparator Input m, is selected as for Single-shot control.

This bit is RES0 if m >= TRCIDR4.NUMPC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCSSPCICR<n>

Must be programmed if implemented and any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

TRCSSPCICR<n> can be accessed through the external debug interface:

ComponentOffset
ETE0x2C0 + 4n

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


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