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TRCVIIECTLR, ViewInst Include/Exclude Control Register

The TRCVIIECTLR characteristics are:

Purpose

Use this to select, or read, the Address Range Comparators for the ViewInst include/exclude function.

Configuration

External register TRCVIIECTLR bits [31:0] are architecturally mapped to AArch64 System register TRCVIIECTLR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMACPAIRS > 0b0000 and ETE is implemented. Otherwise, direct accesses to TRCVIIECTLR are RES0.

Attributes

TRCVIIECTLR is a 32-bit register.

Field descriptions

The TRCVIIECTLR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0EXCLUDE<m>, bit [m+16] RES0INCLUDE<m>, bit [m]

Bits [31:24]

Reserved, RES0.

EXCLUDE<m>, bit [m+16], for m = 0 to 7

Selects which Address Range Comparators are in use with the ViewInst exclude function.

Each bit represents an Address Range Comparator, so bit[m] controls the selection of Address Range Comparator m.

EXCLUDE<m>Meaning
0b0

The address range that Address Range Comparator m defines, is not selected for the ViewInst exclude function.

0b1

The address range that Address Range Comparator m defines, is selected for the ViewInst exclude function.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Bits [15:8]

Reserved, RES0.

INCLUDE<m>, bit [m], for m = 0 to 7

Selects which Address Range Comparators are in use with the ViewInst include function.

Each bit represents an Address Range Comparator, so bit[m] controls the selection of Address Range Comparator m.

Selecting no comparators for the ViewInst include function indicates that all instructions are included by default.

The ViewInst exclude function then indicates which ranges are excluded.

INCLUDE<m>Meaning
0b0

The address range that Address Range Comparator m defines, is not selected for the ViewInst include function.

0b1

The address range that Address Range Comparator m defines, is selected for the ViewInst include function.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCVIIECTLR

Must be programmed if TRCIDR4.NUMACPAIRS > 0b0000.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCVIIECTLR can be accessed through the external debug interface:

ComponentOffset
ETE0x084

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


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