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TRCVIPCSSCTLR, ViewInst Start/Stop PE Comparator Control Register

The TRCVIPCSSCTLR characteristics are:

Purpose

Use this to select, or read, which PE Comparator Inputs can control the ViewInst start/stop function.

Configuration

External register TRCVIPCSSCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCVIPCSSCTLR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMPC > 0b0000 and ETE is implemented. Otherwise, direct accesses to TRCVIPCSSCTLR are RES0.

Attributes

TRCVIPCSSCTLR is a 32-bit register.

Field descriptions

The TRCVIPCSSCTLR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0STOP<m>, bit [m+16] RES0START<m>, bit [m]

Bits [31:24]

Reserved, RES0.

STOP<m>, bit [m+16], for m = 0 to 7

Selects which PE Comparator Inputs are in use with ViewInst start/stop function, for the purpose of stopping trace.

STOP<m>Meaning
0b0

The PE Comparator Input m, is not selected as a stop resource.

0b1

The PE Comparator Input m, is selected as a stop resource.

This bit is RES0 if m >= TRCIDR4.NUMPC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Bits [15:8]

Reserved, RES0.

START<m>, bit [m], for m = 0 to 7

Selects which PE Comparator Inputs are in use with ViewInst start/stop function, for the purpose of starting trace.

START<m>Meaning
0b0

The PE Comparator Input m, is not selected as a start resource.

0b1

The PE Comparator Input m, is selected as a start resource.

This bit is RES0 if m >= TRCIDR4.NUMPC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCVIPCSSCTLR

Must be programmed if TRCIDR4.NUMPC != 0b0000.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCVIPCSSCTLR can be accessed through the external debug interface:

ComponentOffset
ETE0x08C

This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
  • Otherwise access to this register is RW.


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