DBGWCR<n>, Debug Watchpoint Control Registers, n = 0 - 15
The DBGWCR<n> characteristics are:
Purpose
Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>.
Configuration
AArch32 System register DBGWCR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGWCR<n>_EL1[31:0] .
AArch32 System register DBGWCR<n> bits [31:0] are architecturally mapped to External register DBGWCR<n>_EL1[31:0] .
If watchpoint n is not implemented then accesses to this register are UNDEFINED.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
Attributes
DBGWCR<n> is a 32-bit register.
Field descriptions
The DBGWCR<n> bit assignments are:
When the E field is zero, all the other fields in the register are ignored.
Bits [31:29]
Reserved, RES0.
MASK, bits [28:24]
Address mask. Only objects up to 2GB can be watched using a single mask.
MASK | Meaning |
---|---|
0b00000 |
No mask. |
0b00001 |
Reserved. |
0b00010 |
Reserved. |
If programmed with a reserved value, a watchpoint must behave as if either:
- MASK has been programmed with a defined value, which might be 0 (no mask), other than for a direct read of DBGWCRn_EL1.
- The watchpoint is disabled.
Software must not rely on this property because the behavior of reserved values might change in a future revision of the architecture.
Other values mask the corresponding number of address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Bits [23:21]
Reserved, RES0.
WT, bit [20]
Watchpoint type. Possible values are:
WT | Meaning |
---|---|
0b0 |
Unlinked data address match. |
0b1 |
Linked data address match. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
LBN, bits [19:16]
Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
SSC, bits [15:14]
Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.
For more information, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, and 'Reserved DBGBCR<n>.{SSC, HMC, PMC} values' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
HMC, bit [13]
Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2 (AArch32 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
BAS, bits [12:5]
Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n> is being watched.
BAS | Description |
---|---|
0bxxxxxxx1 | Match byte at DBGWVR<n> |
0bxxxxxx1x | Match byte at DBGWVR<n>+1 |
0bxxxxx1xx | Match byte at DBGWVR<n>+2 |
0bxxxx1xxx | Match byte at DBGWVR<n>+3 |
In cases where DBGWVR<n> addresses a double-word:
BAS | Description, if DBGWVR<n>[2] == 0 |
---|---|
0bxxx1xxxx | Match byte at DBGWVR<n>+4 |
0bxx1xxxxx | Match byte at DBGWVR<n>+5 |
0bx1xxxxxx | Match byte at DBGWVR<n>+6 |
0b1xxxxxxx | Match byte at DBGWVR<n>+7 |
If DBGWVR<n>[2] == 1, only BAS[3:0] are used and BAS[7:4] are ignored. Arm deprecates setting DBGWVR<n>[2] == 1.
The valid values for BAS are non-zero binary numbers all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>.BAS values' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2 (AArch32 Self-hosted Debug)
On a Cold reset, this field resets to an architecturally UNKNOWN value.
LSC, bits [4:3]
Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:
LSC | Meaning |
---|---|
0b01 |
Match instructions that load from a watchpointed address. |
0b10 |
Match instructions that store to a watchpointed address. |
0b11 |
Match instructions that load from or store to a watchpointed address. |
All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
PAC, bits [2:1]
Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2 (AArch32 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
E, bit [0]
Enable watchpoint n. Possible values are:
E | Meaning |
---|---|
0b0 |
Watchpoint disabled. |
0b1 |
Watchpoint enabled. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Accessing the DBGWCR<n>
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR[UInt(CRm<3:0>)];
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR[UInt(CRm<3:0>)] = R[t];