SDER, Secure Debug Enable Register
The SDER characteristics are:
Purpose
Controls invasive and non-invasive debug in the Secure EL0 mode.
Configuration
AArch32 System register SDER bits [31:0] are architecturally mapped to AArch64 System register SDER32_EL3[31:0] .
This register is present only when HaveEL(EL3) or the implemented Security state is Secure state. Otherwise, direct accesses to SDER are UNDEFINED.
This register is ignored by the PE when one or more of the following are true:
-
The PE is in Non-secure state.
-
EL1 is using AArch64.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
Attributes
SDER is a 32-bit register.
Field descriptions
The SDER bit assignments are:
Bits [31:2]
Reserved, RES0.
SUNIDEN, bit [1]
Secure User Non-Invasive Debug Enable.
SUNIDEN | Meaning |
---|---|
0b0 |
This bit does not affect Performance Monitors event counting at Secure EL0 |
0b1 |
If EL3 or EL1 is using AArch32, Performance Monitors event counting is allowed in Secure EL0. |
On a Warm reset, this field resets to 0.
SUIDEN, bit [0]
Secure User Invasive Debug Enable.
SUIDEN | Meaning |
---|---|
0b0 |
This bit does not affect the generation of debug exceptions at Secure EL0. |
0b1 |
If EL3 or EL1 is using AArch32, debug exceptions from Secure EL0 are enabled. |
On a Warm reset, this field resets to 0.
Accessing the SDER
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif (!HaveEL(EL3) || !ELUsingAArch32(EL3)) && SCR_EL3.NS == '0' then return SDER; else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return SDER;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif (!HaveEL(EL3) || !ELUsingAArch32(EL3)) && SCR_EL3.NS == '0' then SDER = R[t]; else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; else SDER = R[t];