AMEVTYPER1<n>_EL0, Activity Monitors Event Type Registers 1, n = 0 - 15
The AMEVTYPER1<n>_EL0 characteristics are:
Purpose
Provides information on the events that an auxiliary activity monitor event counter AMEVCNTR1<n>_EL0 counts.
Configuration
AArch64 System register AMEVTYPER1<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER1<n>[31:0] .
AArch64 System register AMEVTYPER1<n>_EL0 bits [31:0] are architecturally mapped to External register AMEVTYPER1<n>[31:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER1<n>_EL0 are UNDEFINED.
Attributes
AMEVTYPER1<n>_EL0 is a 64-bit register.
Field descriptions
The AMEVTYPER1<n>_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | evtCount | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:16]
Reserved, RES0.
evtCount, bits [15:0]
Event to count. The event number of the event that is counted by the auxiliary activity monitor event counter AMEVCNTR1<n>_EL0.
It is IMPLEMENTATION DEFINED what values are supported by each counter.
If software writes a value to this field which is not supported by the corresponding counter AMEVCNTR1<n>_EL0, then:
- It is UNPREDICTABLE which event will be counted.
- The value read back is UNKNOWN.
The event counted by AMEVCNTR1<n>_EL0 might be fixed at implementation. In this case, the field is read-only and writes are UNDEFINED.
If the corresponding counter AMEVCNTR1<n>_EL0 is enabled, writes to this register have UNPREDICTABLE results.
Accessing the AMEVTYPER1<n>_EL0
If <n> is greater than or equal to the number of auxiliary activity monitor event counters, reads and writes of AMEVTYPER1<n>_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.
AMCGCR_EL0.CG1NC identifies the number of auxiliary activity monitor event counters.
Accesses to this register use the following encodings:
MRS <Xt>, AMEVTYPER1<n>_EL0
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b111:n[3] | n[2:0] |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMEVTYPER1_EL0[UInt(CRm<0>:op2<2:0>)]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMEVTYPER1_EL0[UInt(CRm<0>:op2<2:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMEVTYPER1_EL0[UInt(CRm<0>:op2<2:0>)]; elsif PSTATE.EL == EL3 then return AMEVTYPER1_EL0[UInt(CRm<0>:op2<2:0>)];
MSR AMEVTYPER1<n>_EL0, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b111:n[3] | n[2:0] |
if IsHighestEL(PSTATE.EL) then AMEVTYPER1_EL0[UInt(CRm<0>:op2<2:0>)] = X[t]; else UNDEFINED;