TRBLIMITR_EL1, Trace Buffer Limit Address Register
The TRBLIMITR_EL1 characteristics are:
Purpose
Defines the top address for the trace buffer, and controls the trace buffer modes and enable.
Configuration
This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBLIMITR_EL1 are UNDEFINED.
This register is in the Cold reset domain. Some or all RW fields of this register have defined reset values. On a Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
Attributes
TRBLIMITR_EL1 is a 64-bit register.
Field descriptions
The TRBLIMITR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
LIMIT | |||||||||||||||||||||||||||||||
LIMIT | RES0 | nVM | TM | FM | E | ||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LIMIT, bits [63:12]
Trace Buffer Limit pointer address. (TRBLIMITR_EL1.LIMIT << 12) is the address of the last byte in the trace buffer plus one. Bits [11:0] of the Limit pointer address are always zero. If the smallest implemented translation granule is not 4KB, then TRBLIMITR_EL1[N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value Log2(smallest implemented translation granule).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Bits [11:6]
Reserved, RES0.
nVM, bit [5]
Address mode.
nVM | Meaning |
---|---|
0b0 |
The trace buffer pointers are virtual addresses. |
0b1 |
The trace buffer pointers are:
|
On a Cold reset, this field resets to an architecturally UNKNOWN value.
TM, bits [4:3]
Trigger mode.
TM | Meaning |
---|---|
0b00 |
Stop on trigger. Flush then stop collection and raise maintenance interrupt on Trigger Event. |
0b01 |
IRQ on trigger. Continue collection and raise maintenance interrupt on Trigger Event. |
0b11 |
Ignore trigger. Continue collection and do not raise maintenance interrupt on Trigger Event. |
All other values are reserved.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
FM, bits [2:1]
Trace buffer mode.
FM | Meaning |
---|---|
0b00 |
Fill mode. Stop collection and raise maintenance interrupt on current write pointer wrap. |
0b01 |
Wrap mode. Continue collection and raise maintenance interrupt on current write pointer wrap. |
0b11 |
Circular Buffer mode. Continue collection and do not raise maintenance interrupt on current write pointer wrap. |
All other values are reserved.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
E, bit [0]
Trace Buffer Extension enable.
E | Meaning |
---|---|
0b0 |
Trace Buffer Extension disabled. |
0b1 |
Trace Buffer Extension enabled by this control. |
Regardless of the value of this bit, the Trace Buffer Extension is disabled when SelfHostedTraceEnabled() == FALSE. All output is discarded by the Trace Buffer Extension when it is disabled.
On a Cold reset, this field resets to 0.
Accessing the TRBLIMITR_EL1
The PE might ignore a direct write to TRBLIMITR_EL1, other than a direct write that modifies TRBLIMITR_EL1.E, if TRBLIMITR_EL1.E == 1.
Accesses to this register use the following encodings:
MRS <Xt>, TRBLIMITR_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRBLIMITR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRBLIMITR_EL1; elsif PSTATE.EL == EL3 then return TRBLIMITR_EL1;
MSR TRBLIMITR_EL1, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else TRBLIMITR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else TRBLIMITR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRBLIMITR_EL1 = X[t];