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TRBPTR_EL1, Trace Buffer Write Pointer Register

The TRBPTR_EL1 characteristics are:

Purpose

Defines the current write pointer for the trace buffer.

Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBPTR_EL1 are UNDEFINED.

This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.

Attributes

TRBPTR_EL1 is a 64-bit register.

Field descriptions

The TRBPTR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
PTR
PTR
313029282726252423222120191817161514131211109876543210

PTR, bits [63:0]

Trace Buffer current write pointer address.

Defines the virtual address of the next entry to be written to the trace buffer.

The architecture places restrictions on the values that software can write to the pointer.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRBPTR_EL1

The PE might ignore a direct write to TRBPTR_EL1 if TRBLIMITR_EL1.E == 1.

Accesses to this register use the following encodings:

MRS <Xt>, TRBPTR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b001
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBPTR_EL1;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBPTR_EL1;
elsif PSTATE.EL == EL3 then
    return TRBPTR_EL1;
              

MSR TRBPTR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10110b001
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBPTR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBPTR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    TRBPTR_EL1 = X[t];
              


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