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TRBSR_EL1, Trace Buffer Status/syndrome Register

The TRBSR_EL1 characteristics are:

Purpose

Provides syndrome information to software for a trace buffer management event.

Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBSR_EL1 are UNDEFINED.

This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.

Attributes

TRBSR_EL1 is a 64-bit register.

Field descriptions

The TRBSR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
ECRES0IRQTRGWRAPRES0EASRES0MSS

Bits [63:32]

Reserved, RES0.

EC, bits [31:26]

Event class.

ECMeaningMSS
0b100100

Stage 1 data abort on write to trace buffer.

MSS encoding for a stage 1 data abort on write to trace buffer.
0b100101

Stage 2 data abort on write to trace buffer.

MSS encoding for a stage 2 data abort on write to trace buffer.
0b000000

Other trace buffer management event. All trace buffer management events other than those described by the other defined Event class codes.

MSS encoding for an other trace buffer management event.

All other values are reserved.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [25:23]

Reserved, RES0.

IRQ, bit [22]

Maintenance interrupt status.

IRQMeaning
0b0

Maintenance interrupt is not asserted.

0b1

Maintenance interrupt is asserted.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

TRG, bit [21]

Triggered.

TRGMeaning
0b0

No Detected Trigger has been observed since this bit was last cleared to zero.

0b1

A Detected Trigger has been observed since this bit was last cleared to zero.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

WRAP, bit [20]

Wrapped.

WRAPMeaning
0b0

The current write pointer has not wrapped since this bit was last cleared to zero.

0b1

The current write pointer has wrapped since this bit was last cleared to zero.

For each byte of trace the Trace Buffer Extension Accepts and writes to the trace buffer at the address in the current write pointer, if the current write pointer is equal to the Limit pointer minus one, the current write pointer is wrapped by setting it to the Base pointer, and this bit is set to 1.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bit [19]

Reserved, RES0.

EA, bit [18]

External Abort.

EAMeaning
0b0

An External Abort has not been asserted.

0b1

An External Abort has been asserted and detected by the Trace Buffer Extension.

This bit is RES0 if the PE never sets this bit as the result of an External Abort.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

S, bit [17]

Stopped.

SMeaning
0b0

Collection has not been stopped.

0b1

Collection is stopped.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bit [16]

Reserved, RES0.

MSS, bits [15:0]

Management Event Specific Syndrome. Contains syndrome specific to the management event.

The syndrome contents for each management event are described in the following sections.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

MSS encoding for an other trace buffer management event.

Bits [15:6]

Reserved, RES0.

BSC, bits [5:0]

Trace buffer status code.

BSCMeaning
0b000000

Collection not stopped.

0b000001

Trace buffer filled. Collection stopped because the current write pointer wrapped to the base pointer and the trace buffer mode is Fill mode.

0b000010

Trigger Event. Collection stopped because of a Trigger Event. See TRBTRG_EL1 for more information.

All other values are reserved.

MSS encoding for a stage 1 data abort on write to trace buffer.

Bits [15:6]

Reserved, RES0.

FSC, bits [5:0]

Fault status code.

FSCMeaning
0b000000

Address Size fault, level 0.

0b000001

Address Size fault, level 1.

0b000010

Address Size fault, level 2.

0b000011

Address Size fault, level 3.

0b000100

Translation fault, level 0.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001000

Access Flag fault, level 0.

0b001001

Access Flag fault, level 1.

0b001010

Access Flag fault, level 2.

0b001011

Access Flag fault, level 3.

0b001100

Permission fault, level 0.

0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External Abort on write.

0b010001

Asynchronous External Abort on write.

0b010100

Synchronous External Abort on translation table walk or hardware update of translation table, level 0.

0b010101

Synchronous External Abort on translation table walk or hardware update of translation table, level 1.

0b010110

Synchronous External Abort on translation table walk or hardware update of translation table, level 2.

0b010111

Synchronous External Abort on translation table walk or hardware update of translation table, level 3.

0b100001

Alignment fault.

0b110000

TLB Conflict fault.

All other values are reserved.

MSS encoding for a stage 2 data abort on write to trace buffer.

    1514131211109876543210
    RES0FSC
    313029282726252423222120191817161514131211109876543210

Bits [15:6]

Reserved, RES0.

FSC, bits [5:0]

Fault status code.

FSCMeaning
0b000000

Address Size fault, level 0.

0b000001

Address Size fault, level 1.

0b000010

Address Size fault, level 2.

0b000011

Address Size fault, level 3.

0b000100

Translation fault, level 0.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001000

Access Flag fault, level 0.

0b001001

Access Flag fault, level 1.

0b001010

Access Flag fault, level 2.

0b001011

Access Flag fault, level 3.

0b001100

Permission fault, level 0.

0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External Abort on write.

0b010001

Asynchronous External Abort on write.

0b010100

Synchronous External Abort on translation table walk or hardware update of translation table, level 0.

0b010101

Synchronous External Abort on translation table walk or hardware update of translation table, level 1.

0b010110

Synchronous External Abort on translation table walk or hardware update of translation table, level 2.

0b010111

Synchronous External Abort on translation table walk or hardware update of translation table, level 3.

0b100001

Alignment fault.

0b110000

TLB Conflict fault.

All other values are reserved.

Accessing the TRBSR_EL1

The PE might ignore a direct write to TRBSR_EL1 if TRBLIMITR_EL1.E == 1.

Accesses to this register use the following encodings:

MRS <Xt>, TRBSR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b011
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBSR_EL1;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBSR_EL1;
elsif PSTATE.EL == EL3 then
    return TRBSR_EL1;
              

MSR TRBSR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10110b011
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBSR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBSR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    TRBSR_EL1 = X[t];
              


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