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TRCIDR2, ID Register 2

The TRCIDR2 characteristics are:

Purpose

Returns the tracing capabilities of the trace unit.

Configuration

AArch64 System register TRCIDR2 bits [31:0] are architecturally mapped to External register TRCIDR2[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR2 are UNDEFINED.

Attributes

TRCIDR2 is a 64-bit register.

Field descriptions

The TRCIDR2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
WFXMODEVMIDOPTCCSIZEDVSIZEDASIZEVMIDSIZECIDSIZEIASIZE
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

WFXMODE, bit [31]

Indicates whether WFI and WFE instructions are classified as P0 instructions:

WFXMODEMeaning
0b0

WFI and WFE instructions are not classified as P0 instructions.

0b1

WFI and WFE instructions are classified as P0 instructions.

VMIDOPT, bits [30:29]

When TRCIDR2.VMIDSIZE != 0b00000:

Indicates the options for Virtual context identifier selection.

VMIDOPTMeaning
0b00

Virtual context identifier selection not supported. TRCCONFIGR.VMIDOPT is RES0.

0b01

Virtual context identifier selection supported. TRCCONFIGR.VMIDOPT is implemented.

0b10

Virtual context identifier selection not supported. TRCCONFIGR.VMIDOPT is RES1.

All other values are reserved.

This field reads as 0b10.


Otherwise:

Reserved, RES0.

CCSIZE, bits [28:25]

When TRCIDR0.TRCCCI == 0b1:

Indicates the size of the cycle counter.

CCSIZEMeaning
0b0000

The cycle counter is 12 bits in length.

0b0001

The cycle counter is 13 bits in length.

0b0010

The cycle counter is 14 bits in length.

0b0011

The cycle counter is 15 bits in length.

0b0100

The cycle counter is 16 bits in length.

0b0101

The cycle counter is 17 bits in length.

0b0110

The cycle counter is 18 bits in length.

0b0111

The cycle counter is 19 bits in length.

0b1000

The cycle counter is 20 bits in length.

All other values are reserved.


Otherwise:

Reserved, RES0.

DVSIZE, bits [24:20]

When TRCIDR0.TRCDATA != 0b00:

Indicates the data value size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

DVSIZEMeaning
0b00000

Data value tracing not implemented.

0b00100

Data value tracing has a maximum of 32-bit data values.

0b01000

Data value tracing has a maximum of 64-bit data values.

All other values are reserved.


Otherwise:

Reserved, RES0.

DASIZE, bits [19:15]

When TRCIDR0.TRCDATA != 0b00:

Indicates the data address size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

DASIZEMeaning
0b00000

Data address tracing not implemented.

0b00100

Data address tracing has a maximum of 32-bit data addresses.

0b01000

Data address tracing has a maximum of 64-bit data addresses.

All other values are reserved.


Otherwise:

Reserved, RES0.

VMIDSIZE, bits [14:10]

When HaveEL(EL2):

Indicates the trace unit Virtual context identifier size.

VMIDSIZEMeaning
0b00000

Virtual context identifier tracing is not supported.

0b00001

8-bit Virtual context identifier size.

0b00010

16-bit Virtual context identifier size.

0b00100

32-bit Virtual context identifier size.

All other values are reserved.

This field reads as 0b00100.


Otherwise:

Reserved, RES0.

CIDSIZE, bits [9:5]

Indicates the Context identifier size.

CIDSIZEMeaning
0b00000

Context identifier tracing is not supported.

0b00100

32-bit Context identifier size.

All other values are reserved.

This field reads as 0b00100.

IASIZE, bits [4:0]

Virtual instruction address size.

IASIZEMeaning
0b00100

Maximum of 32-bit instruction address size.

0b01000

Maximum of 64-bit instruction address size.

All other values are reserved.

This field reads as 0b01000.

Accessing the TRCIDR2

Accesses to this register use the following encodings:

MRS <Xt>, TRCIDR2

op0op1CRnCRmop2
0b100b0010b00000b10100b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR2;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR2;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR2;
              


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