AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n = 0 - 15
The AMEVTYPER0<n> characteristics are:
Purpose
Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n> counts.
Configuration
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch64 System register AMEVTYPER0<n>_EL0[31:0] .
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER0<n>[31:0] .
The power domain of AMEVTYPER0<n> is IMPLEMENTATION DEFINED.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n> are RES0.
Attributes
AMEVTYPER0<n> is a 32-bit register.
Field descriptions
The AMEVTYPER0<n> bit assignments are:
Bits [31:25]
Reserved, RAZ.
Bits [24:16]
Reserved, RES0.
evtCount, bits [15:0]
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
evtCount | Meaning | Applies when |
---|---|---|
0x0011 |
Processor frequency cycles | When n == 0 |
0x4004 |
Constant frequency cycles | When n == 1 |
0x0008 |
Instructions retired | When n == 2 |
0x4005 |
Memory stall cycles | When n == 3 |
Accessing the AMEVTYPER0<n>
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVTYPER0<n> are CONSTRAINED UNPREDICTABLE, and accesses to the register behave as RAZ/WI.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
AMEVTYPER0<n> can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
AMU | 0x400 + 4n | AMEVTYPER0<n> |
Accesses on this interface are RO.