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ERRCRICR1, Critical Error Interrupt Configuration Register 1

The ERRCRICR1 characteristics are:


Interrupt configuration register.


External register ERRCRICR1 bits [31:0] are architecturally mapped to External register ERRIRQCR5[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERRCRICR1 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.


ERRCRICR1 is a 32-bit register.

Field descriptions

The ERRCRICR1 bit assignments are:


DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERRCRICR1

ERRCRICR1 can be accessed through the memory-mapped interfaces:


Accesses on this interface are RW.