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ERRFHICR0, Fault-Handling Interrupt Configuration Register 0

The ERRFHICR0 characteristics are:


Interrupt configuration register.


External register ERRFHICR0 is architecturally mapped to External register ERRIRQCR0.

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRFHICR0 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.


ERRFHICR0 is a 64-bit register.

Field descriptions

The ERRFHICR0 bit assignments are:


Bits [63:56]

Reserved, RES0.

ADDR, bits [55:2]

Message Signaled Interrupt address.

Specifies the address that the component writes to when signaling an interrupt.

The size of a physical address is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [1:0]

Reserved, RES0.

Accessing the ERRFHICR0

ERRFHICR0 can be accessed through the memory-mapped interfaces:


Accesses on this interface are RW.

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