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ERRPIDR4, Peripheral Identification Register 4

The ERRPIDR4 characteristics are:


Provides discovery information about the component.

For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.


Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR4 are RES0.


ERRPIDR4 is a 32-bit register.

Field descriptions

The ERRPIDR4 bit assignments are:


Bits [31:8]

Reserved, RES0.

SIZE, bits [7:4]

Size of the component. The distance from the start of the address space used by this component to the end of the component identification registers.

If the value of this field is non-zero, then the component occupies 2ERRPIDR4.SIZE 4KB blocks.


One of the following is true:

  • The component uses a single 4KB block.

  • The component uses an IMPLEMENTATION DEFINED number of 4KB blocks.

Using this bit field to indicate the size of the component is deprecated. This bit field might not correctly indicate the size of the component.

Arm recommends that software determine the size of the component from the Unique Component Identifier fields, and other IMPLEMENTATION DEFINED registers in the component.

This register reads as an IMPLEMENTATION DEFINED value.

DES_2, bits [3:0]

Designer, JEP106 continuation code. This is the JEDEC-assigned JEP106 bank identifier for the designer of the component, minus 1.

The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component.

This field reads as an IMPLEMENTATION DEFINED value.


For a component designed by Arm Limited, the JEP106 bank is 5, meaning this field has the value 0x4.

Accessing the ERRPIDR4

ERRPIDR4 can be accessed through the memory-mapped interfaces:


Accesses on this interface are RO.

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