GICD_ICFGR<n>, Interrupt Configuration Registers, n = 0 - 63
The GICD_ICFGR<n> characteristics are:
Determines whether the corresponding interrupt is edge-triggered or level-sensitive.
RW fields in this register reset to architecturally UNKNOWN values.
These registers are available in all GIC configurations. If the GIC implementation supports two Security states, these registers are Common.
GICD_ICFGR1 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICFGR1 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
For SGIs and PPIs:
- When ARE is 1 for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case.
- Equivalent functionality is provided by GICR_ICFGR<n>
For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
For SGIs, Int_config fields are RO, meaning that GICD_ICFGR0 is RO.
Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE.
Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state.
Fields corresponding to unimplemented interrupts are RAZ/WI.
GICD_ICFGR<n> is a 32-bit register.
The GICD_ICFGR<n> bit assignments are:
|Int_config<x>, bits [2x+1:2x], for x = 0 to 15|
Int_config<x>, bits [2x+1:2x], for x = 0 to 15
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config (bit [2x]) is RES0.
Possible values of Int_config (bit [2x+1]) are:
Corresponding interrupt is level-sensitive.
Corresponding interrupt is edge-triggered.
For SGIs, Int_config is RAO/WI.
For SPIs and PPIs, Int_config is programmable unless the implementation supports two Security states and the bit corresponds to a Group 0 or Secure Group 1 interrupt, in which case the bit is RAZ/WI to Non-secure accesses.
This field resets to an architecturally UNKNOWN value.
Accessing the GICD_ICFGR<n>
GICD_ICFGR<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0C00 + 4n||GICD_ICFGR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.